Lines Matching refs:I2C_WRITE
79 #define I2C_WRITE(sc, reg, val) \ macro
191 I2C_WRITE(sc, I2C_CLK_DIVISOR_REG, in tegra_i2c_init()
195 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); in tegra_i2c_init()
196 I2C_WRITE(sc, I2C_CNFG_REG, in tegra_i2c_init()
199 I2C_WRITE(sc, I2C_FIFO_CONTROL_REG, in tegra_i2c_init()
203 I2C_WRITE(sc, I2C_BUS_CONFIG_LOAD_REG, in tegra_i2c_init()
223 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); in tegra_i2c_intr()
254 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, in tegra_i2c_exec()
294 I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0); in tegra_i2c_exec()
361 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); in tegra_i2c_write()
364 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, in tegra_i2c_write()
374 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, in tegra_i2c_write()
377 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, in tegra_i2c_write()
401 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data); in tegra_i2c_write()
419 I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus); in tegra_i2c_read()
422 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, in tegra_i2c_read()
432 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, in tegra_i2c_read()
435 I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, in tegra_i2c_read()