322 #define CLK_MUX(_name, _reg, _bits, _p) {			\  argument
329 			.bits = (_bits)				\
344 #define CLK_DIV(_name, _parent, _reg, _bits) {			\  argument
350 			.bits = (_bits)				\
355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) {		\  argument
363 			.bits = (_bits),			\
368 #define CLK_GATE_L(_name, _parent, _bits) 			\  argument
371 		 _bits)
373 #define CLK_GATE_H(_name, _parent, _bits) 			\  argument
376 		 _bits)
378 #define CLK_GATE_U(_name, _parent, _bits) 			\  argument
381 		 _bits)
383 #define CLK_GATE_V(_name, _parent, _bits) 			\  argument
386 		 _bits)
388 #define CLK_GATE_W(_name, _parent, _bits) 			\  argument
391 		 _bits)
393 #define CLK_GATE_X(_name, _parent, _bits) 			\  argument
396 		 _bits)
398 #define CLK_GATE_Y(_name, _parent, _bits) 			\  argument
401 		 _bits)
404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits)		\  argument
405 	CLK_GATE(_name, _parent, _reg, _reg, _bits)