Lines Matching defs:_bits
322 #define CLK_MUX(_name, _reg, _bits, _p) { \ argument
344 #define CLK_DIV(_name, _parent, _reg, _bits) { \ argument
355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \ argument
368 #define CLK_GATE_L(_name, _parent, _bits) \ argument
373 #define CLK_GATE_H(_name, _parent, _bits) \ argument
378 #define CLK_GATE_U(_name, _parent, _bits) \ argument
383 #define CLK_GATE_V(_name, _parent, _bits) \ argument
388 #define CLK_GATE_W(_name, _parent, _bits) \ argument
393 #define CLK_GATE_X(_name, _parent, _bits) \ argument
398 #define CLK_GATE_Y(_name, _parent, _bits) \ argument
404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \ argument