Lines Matching refs:tclk

978 	struct tegra_clk *tclk;  in tegra124_car_clock_decode()  local
986 tclk = tegra124_car_clock_find_by_id(clock_id); in tegra124_car_clock_decode()
987 if (tclk) in tegra124_car_clock_decode()
988 return TEGRA_CLK_BASE(tclk); in tegra124_car_clock_decode()
996 struct tegra_clk *tclk; in tegra124_car_clock_get() local
998 tclk = tegra124_car_clock_find(name); in tegra124_car_clock_get()
999 if (tclk == NULL) in tegra124_car_clock_get()
1002 atomic_inc_uint(&tclk->refcnt); in tegra124_car_clock_get()
1004 return TEGRA_CLK_BASE(tclk); in tegra124_car_clock_get()
1010 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); in tegra124_car_clock_put() local
1012 KASSERT(tclk->refcnt > 0); in tegra124_car_clock_put()
1014 atomic_dec_uint(&tclk->refcnt); in tegra124_car_clock_put()
1019 struct tegra_clk *tclk) in tegra124_car_clock_get_rate_pll() argument
1021 struct tegra_pll_clk *tpll = &tclk->u.pll; in tegra124_car_clock_get_rate_pll()
1028 KASSERT(tclk->type == TEGRA_CLK_PLL); in tegra124_car_clock_get_rate_pll()
1030 tclk_parent = tegra124_car_clock_find(tclk->parent); in tegra124_car_clock_get_rate_pll()
1051 struct tegra_clk *tclk, u_int rate) in tegra124_car_clock_set_rate_pll() argument
1053 struct tegra_pll_clk *tpll = &tclk->u.pll; in tegra124_car_clock_set_rate_pll()
1059 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); in tegra124_car_clock_set_rate_pll()
1130 struct tegra_clk *tclk, struct tegra_clk *tclk_parent) in tegra124_car_clock_set_parent_mux() argument
1132 struct tegra_mux_clk *tmux = &tclk->u.mux; in tegra124_car_clock_set_parent_mux()
1138 KASSERT(tclk->type == TEGRA_CLK_MUX); in tegra124_car_clock_set_parent_mux()
1186 struct tegra_clk *tclk) in tegra124_car_clock_get_parent_mux() argument
1188 struct tegra_mux_clk *tmux = &tclk->u.mux; in tegra124_car_clock_get_parent_mux()
1192 KASSERT(tclk->type == TEGRA_CLK_MUX); in tegra124_car_clock_get_parent_mux()
1208 struct tegra_clk *tclk) in tegra124_car_clock_get_rate_fixed_div() argument
1210 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div; in tegra124_car_clock_get_rate_fixed_div()
1213 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); in tegra124_car_clock_get_rate_fixed_div()
1233 struct tegra_clk *tclk) in tegra124_car_clock_get_rate_div() argument
1235 struct tegra_div_clk *tdiv = &tclk->u.div; in tegra124_car_clock_get_rate_div()
1241 KASSERT(tclk->type == TEGRA_CLK_DIV); in tegra124_car_clock_get_rate_div()
1243 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); in tegra124_car_clock_get_rate_div()
1280 struct tegra_clk *tclk, u_int rate) in tegra124_car_clock_set_rate_div() argument
1282 struct tegra_div_clk *tdiv = &tclk->u.div; in tegra124_car_clock_set_rate_div()
1289 KASSERT(tclk->type == TEGRA_CLK_DIV); in tegra124_car_clock_set_rate_div()
1291 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk)); in tegra124_car_clock_set_rate_div()
1363 struct tegra_clk *tclk, bool enable) in tegra124_car_clock_enable_gate() argument
1365 struct tegra_gate_clk *tgate = &tclk->u.gate; in tegra124_car_clock_enable_gate()
1370 KASSERT(tclk->type == TEGRA_CLK_GATE); in tegra124_car_clock_enable_gate()
1403 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); in tegra124_car_clock_get_rate() local
1406 switch (tclk->type) { in tegra124_car_clock_get_rate()
1408 return tclk->u.fixed.rate; in tegra124_car_clock_get_rate()
1410 return tegra124_car_clock_get_rate_pll(priv, tclk); in tegra124_car_clock_get_rate()
1418 return tegra124_car_clock_get_rate_fixed_div(priv, tclk); in tegra124_car_clock_get_rate()
1420 return tegra124_car_clock_get_rate_div(priv, tclk); in tegra124_car_clock_get_rate()
1422 panic("tegra124: unknown tclk type %d", tclk->type); in tegra124_car_clock_get_rate()
1429 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); in tegra124_car_clock_set_rate() local
1434 switch (tclk->type) { in tegra124_car_clock_set_rate()
1443 rate * tclk->u.fixed_div.div); in tegra124_car_clock_set_rate()
1447 return tegra124_car_clock_set_rate_pll(priv, tclk, rate); in tegra124_car_clock_set_rate()
1449 return tegra124_car_clock_set_rate_div(priv, tclk, rate); in tegra124_car_clock_set_rate()
1451 panic("tegra124: unknown tclk type %d", tclk->type); in tegra124_car_clock_set_rate()
1458 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); in tegra124_car_clock_enable() local
1461 if (tclk->type != TEGRA_CLK_GATE) { in tegra124_car_clock_enable()
1468 return tegra124_car_clock_enable_gate(priv, tclk, true); in tegra124_car_clock_enable()
1474 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); in tegra124_car_clock_disable() local
1476 if (tclk->type != TEGRA_CLK_GATE) in tegra124_car_clock_disable()
1479 return tegra124_car_clock_enable_gate(priv, tclk, false); in tegra124_car_clock_disable()
1486 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); in tegra124_car_clock_set_parent() local
1490 if (tclk->type != TEGRA_CLK_MUX) { in tegra124_car_clock_set_parent()
1498 return tegra124_car_clock_set_parent_mux(priv, tclk, tclk_parent); in tegra124_car_clock_set_parent()
1504 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk); in tegra124_car_clock_get_parent() local
1507 switch (tclk->type) { in tegra124_car_clock_get_parent()
1513 if (tclk->parent) { in tegra124_car_clock_get_parent()
1514 tclk_parent = tegra124_car_clock_find(tclk->parent); in tegra124_car_clock_get_parent()
1518 tclk_parent = tegra124_car_clock_get_parent_mux(priv, tclk); in tegra124_car_clock_get_parent()