310 #define CLK_MUX(_name, _reg, _bits, _p) {			\  argument
317 			.bits = (_bits)				\
332 #define CLK_DIV(_name, _parent, _reg, _bits) {			\  argument
338 			.bits = (_bits)				\
343 #define CLK_GATE(_name, _parent, _set, _clr, _bits) {		\  argument
351 			.bits = (_bits),			\
356 #define CLK_GATE_L(_name, _parent, _bits) 			\  argument
359 		 _bits)
361 #define CLK_GATE_H(_name, _parent, _bits) 			\  argument
364 		 _bits)
366 #define CLK_GATE_U(_name, _parent, _bits) 			\  argument
369 		 _bits)
371 #define CLK_GATE_V(_name, _parent, _bits) 			\  argument
374 		 _bits)
376 #define CLK_GATE_W(_name, _parent, _bits) 			\  argument
379 		 _bits)
381 #define CLK_GATE_X(_name, _parent, _bits) 			\  argument
384 		 _bits)
386 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits)		\  argument
387 	CLK_GATE(_name, _parent, _reg, _reg, _bits)