Lines Matching refs:m32r_cgen_ifld_table

263 const CGEN_IFLD m32r_cgen_ifld_table[] =  variable
317     { 0, { &m32r_cgen_ifld_table[M32R_F_NIL] } },
321     { 0, { &m32r_cgen_ifld_table[M32R_F_R2] } },
325     { 0, { &m32r_cgen_ifld_table[M32R_F_R1] } },
329     { 0, { &m32r_cgen_ifld_table[M32R_F_R1] } },
333     { 0, { &m32r_cgen_ifld_table[M32R_F_R2] } },
337     { 0, { &m32r_cgen_ifld_table[M32R_F_R2] } },
341     { 0, { &m32r_cgen_ifld_table[M32R_F_R1] } },
345     { 0, { &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
349     { 0, { &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
353     { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
357     { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
361     { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
365     { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
369     { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
373     { 0, { &m32r_cgen_ifld_table[M32R_F_IMM1] } },
377     { 0, { &m32r_cgen_ifld_table[M32R_F_ACCD] } },
381     { 0, { &m32r_cgen_ifld_table[M32R_F_ACCS] } },
385     { 0, { &m32r_cgen_ifld_table[M32R_F_ACC] } },
393     { 0, { &m32r_cgen_ifld_table[M32R_F_HI16] } },
397     { 0, { &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
401     { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
405     { 0, { &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
409     { 0, { &m32r_cgen_ifld_table[M32R_F_DISP8] } },
413     { 0, { &m32r_cgen_ifld_table[M32R_F_DISP16] } },
417     { 0, { &m32r_cgen_ifld_table[M32R_F_DISP24] } },
1256   cd->ifld_table = & m32r_cgen_ifld_table[0];  in build_ifield_table()