Lines Matching refs:code

33 @table @code
35 @cindex @code{-mcpu=} command-line option, ARM
41 @code{arm1},
42 @code{arm2},
43 @code{arm250},
44 @code{arm3},
45 @code{arm6},
46 @code{arm60},
47 @code{arm600},
48 @code{arm610},
49 @code{arm620},
50 @code{arm7},
51 @code{arm7m},
52 @code{arm7d},
53 @code{arm7dm},
54 @code{arm7di},
55 @code{arm7dmi},
56 @code{arm70},
57 @code{arm700},
58 @code{arm700i},
59 @code{arm710},
60 @code{arm710t},
61 @code{arm720},
62 @code{arm720t},
63 @code{arm740t},
64 @code{arm710c},
65 @code{arm7100},
66 @code{arm7500},
67 @code{arm7500fe},
68 @code{arm7t},
69 @code{arm7tdmi},
70 @code{arm7tdmi-s},
71 @code{arm8},
72 @code{arm810},
73 @code{strongarm},
74 @code{strongarm1},
75 @code{strongarm110},
76 @code{strongarm1100},
77 @code{strongarm1110},
78 @code{arm9},
79 @code{arm920},
80 @code{arm920t},
81 @code{arm922t},
82 @code{arm940t},
83 @code{arm9tdmi},
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
86 @code{arm9e},
87 @code{arm926e},
88 @code{arm926ej-s},
89 @code{arm946e-r0},
90 @code{arm946e},
91 @code{arm946e-s},
92 @code{arm966e-r0},
93 @code{arm966e},
94 @code{arm966e-s},
95 @code{arm968e-s},
96 @code{arm10t},
97 @code{arm10tdmi},
98 @code{arm10e},
99 @code{arm1020},
100 @code{arm1020t},
101 @code{arm1020e},
102 @code{arm1022e},
103 @code{arm1026ej-s},
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
109 @code{arm1136j-s},
110 @code{arm1136jf-s},
111 @code{arm1156t2-s},
112 @code{arm1156t2f-s},
113 @code{arm1176jz-s},
114 @code{arm1176jzf-s},
115 @code{mpcore},
116 @code{mpcorenovfp},
117 @code{cortex-a5},
118 @code{cortex-a7},
119 @code{cortex-a8},
120 @code{cortex-a9},
121 @code{cortex-a15},
122 @code{cortex-a17},
123 @code{cortex-a32},
124 @code{cortex-a35},
125 @code{cortex-a53},
126 @code{cortex-a55},
127 @code{cortex-a57},
128 @code{cortex-a72},
129 @code{cortex-a73},
130 @code{cortex-a75},
131 @code{cortex-a76},
132 @code{cortex-a76ae},
133 @code{cortex-a77},
134 @code{cortex-a78},
135 @code{cortex-a78ae},
136 @code{cortex-a78c},
137 @code{cortex-a710},
138 @code{ares},
139 @code{cortex-r4},
140 @code{cortex-r4f},
141 @code{cortex-r5},
142 @code{cortex-r7},
143 @code{cortex-r8},
144 @code{cortex-r52},
145 @code{cortex-r52plus},
146 @code{cortex-m35p},
147 @code{cortex-m33},
148 @code{cortex-m23},
149 @code{cortex-m7},
150 @code{cortex-m4},
151 @code{cortex-m3},
152 @code{cortex-m1},
153 @code{cortex-m0},
154 @code{cortex-m0plus},
155 @code{cortex-x1},
156 @code{cortex-x1c},
157 @code{exynos-m1},
158 @code{marvell-pj4},
159 @code{marvell-whitney},
160 @code{neoverse-n1},
161 @code{neoverse-n2},
162 @code{neoverse-v1},
163 @code{xgene1},
164 @code{xgene2},
165 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
166 @code{i80200} (Intel XScale processor)
167 @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
169 @code{xscale}.
170 The special name @code{all} may be used to allow the
175 co-processor instruction space.  For example, @code{-mcpu=arm920+maverick}
176 is equivalent to specifying @code{-mcpu=ep9312}.
178 Multiple extensions may be specified, separated by a @code{+}.  The
185 This is done be prepending @code{no} to the option that adds the extension.
188 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
192 @code{bf16} (BFloat16 extensions for v8.6-A architecture),
193 @code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture),
194 @code{crc}
195 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
196 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
197 @code{fp} (Floating Point Extensions for v8-A architecture),
198 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
199 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, impl…
200 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
201 @code{iwmmxt},
202 @code{iwmmxt2},
203 @code{xscale},
204 @code{maverick},
205 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
207 @code{os} (Operating System for v6M architecture),
208 @code{predres} (Execution and Data Prediction Restriction Instruction for
210 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
212 @code{sec} (Security Extensions for v6K and v7-A architectures),
213 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
214 @code{virt} (Virtualization Extensions for v7-A architecture, implies
215 @code{idiv}),
216 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
217 @code{ras} (Reliability, Availability and Serviceability extensions
219 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
220 @code{simd})
222 @code{xscale}.
224 @cindex @code{-march=} command-line option, ARM
230 @code{armv1},
231 @code{armv2},
232 @code{armv2a},
233 @code{armv2s},
234 @code{armv3},
235 @code{armv3m},
236 @code{armv4},
237 @code{armv4xm},
238 @code{armv4t},
239 @code{armv4txm},
240 @code{armv5},
241 @code{armv5t},
242 @code{armv5txm},
243 @code{armv5te},
244 @code{armv5texp},
245 @code{armv6},
246 @code{armv6j},
247 @code{armv6k},
248 @code{armv6z},
249 @code{armv6kz},
250 @code{armv6-m},
251 @code{armv6s-m},
252 @code{armv7},
253 @code{armv7-a},
254 @code{armv7ve},
255 @code{armv7-r},
256 @code{armv7-m},
257 @code{armv7e-m},
258 @code{armv8-a},
259 @code{armv8.1-a},
260 @code{armv8.2-a},
261 @code{armv8.3-a},
262 @code{armv8-r},
263 @code{armv8.4-a},
264 @code{armv8.5-a},
265 @code{armv8-m.base},
266 @code{armv8-m.main},
267 @code{armv8.1-m.main},
268 @code{armv8.6-a},
269 @code{armv8.7-a},
270 @code{armv8.8-a},
271 @code{armv8.9-a},
272 @code{armv9-a},
273 @code{armv9.1-a},
274 @code{armv9.2-a},
275 @code{armv9.3-a},
276 @code{armv9.4-a},
277 @code{iwmmxt},
278 @code{iwmmxt2}
280 @code{xscale}.
281 If both @code{-mcpu} and
282 @code{-march} are specified, the assembler will use
283 the setting for @code{-mcpu}.
288 @code{-mfpu} option, the union of both feature enablement is taken.
291 …code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @cod…
294 @item @code{+fp}: Enables VFPv2 instructions.
295 @item @code{+nofp}: Disables all FPU instrunctions.
298 For @code{armv7}:
301 @item @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
302 @item @code{+nofp}: Disables all FPU instructions.
305 For @code{armv7-a}:
308 @item @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
309 @item @code{+vfpv3-d16}: Alias for @code{+fp}.
310 @item @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
311 @item @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
313 @item @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
315 @item @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
316 @item @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
317 @item @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
319 @item @code{+neon}: Alias for @code{+simd}.
320 @item @code{+neon-vfpv3}: Alias for @code{+simd}.
321 @item @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
323 @item @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
325 @item @code{+mp}: Enables Multiprocessing Extensions.
326 @item @code{+sec}: Enables Security Extensions.
327 @item @code{+nofp}: Disables all FPU and NEON instructions.
328 @item @code{+nosimd}: Disables all NEON instructions.
331 For @code{armv7ve}:
334 @item @code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
335 @item @code{+vfpv4-d16}: Alias for @code{+fp}.
336 @item @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
337 @item @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
338 @item @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
340 @item @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
342 @item @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
343 @item @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
345 @item @code{+neon-vfpv4}: Alias for @code{+simd}.
346 @item @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
348 @item @code{+neon-vfpv3}: Alias for @code{+neon}.
349 @item @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
352 @item @code{+nofp}: Disables all FPU and NEON instructions.
353 @item @code{+nosimd}: Disables all NEON instructions.
356 For @code{armv7-r}:
359 @item @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
361 @item @code{+vfpv3xd}: Alias for @code{+fp.sp}.
362 @item @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
363 @item @code{+vfpv3-d16}: Alias for @code{+fp}.
364 @item @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
366 @item @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
368 @item @code{+idiv}: Enables integer division instructions in ARM mode.
369 @item @code{+nofp}: Disables all FPU instructions.
372 For @code{armv7e-m}:
375 @item @code{+fp}: Enables single-precision only VFPv4 instructions with 16
377 @item @code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
378 @item @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
380 @item @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
381 @item @code{+fpv5-d16"}: Alias for @code{+fp.dp}.
382 @item @code{+nofp}: Disables all FPU instructions.
385 For @code{armv8-m.main}:
388 @item @code{+dsp}: Enables DSP Extension.
389 @item @code{+fp}: Enables single-precision only VFPv5 instructions with 16
391 @item @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
392 @item @code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0),
393 @item @code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1),
394 @item @code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2),
395 @item @code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3),
396 @item @code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4),
397 @item @code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5),
398 @item @code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6),
399 @item @code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7),
400 @item @code{+nofp}: Disables all FPU instructions.
401 @item @code{+nodsp}: Disables DSP Extension.
404 For @code{armv8.1-m.main}:
407 @item @code{+dsp}: Enables DSP Extension.
408 @item @code{+fp}: Enables single and half precision scalar Floating Point Extensions
410 @item @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
411 Armv8.1-M Mainline, implies @code{+fp}.
412 @item @code{+mve}: Enables integer only M-profile Vector Extension for
413 Armv8.1-M Mainline, implies @code{+dsp}.
414 @item @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for
415 Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}.
416 @item @code{+nofp}: Disables all FPU instructions.
417 @item @code{+nodsp}: Disables DSP Extension.
418 @item @code{+nomve}: Disables all M-profile Vector Extensions.
421 For @code{armv8-a}:
424 @item @code{+crc}: Enables CRC32 Extension.
425 @item @code{+simd}: Enables VFP and NEON for Armv8-A.
426 @item @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies @code{+simd}.
427 @item @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
428 @item @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
430 @item @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
431 @item @code{+nocrypto}: Disables Cryptography Extensions.
434 For @code{armv8.1-a}:
437 @item @code{+simd}: Enables VFP and NEON for Armv8.1-A.
438 @item @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies @code{+simd}.
439 @item @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
440 @item @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
442 @item @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
443 @item @code{+nocrypto}: Disables Cryptography Extensions.
446 For @code{armv8.2-a} and @code{armv8.3-a}:
449 @item @code{+simd}: Enables VFP and NEON for Armv8.1-A.
450 @item @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
451 @item @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
452 for Armv8.2-A, implies @code{+fp16}.
453 @item @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies @code{+simd}.
454 @item @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies @code{+simd}.
455 @item @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
456 @item @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
458 @item @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
459 @item @code{+nocrypto}: Disables Cryptography Extensions.
462 For @code{armv8.4-a}:
465 @item @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
467 @item @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
468 Variant Extensions for Armv8.2-A, implies @code{+simd}.
469 @item @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies @code{+simd}.
470 @item @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
471 @item @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
473 @item @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
474 @item @code{+nocryptp}: Disables Cryptography Extensions.
477 For @code{armv8.5-a}:
480 @item @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
482 @item @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
483 Variant Extensions for Armv8.2-A, implies @code{+simd}.
484 @item @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies @code{+simd}.
485 @item @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
486 @item @code{+nocryptp}: Disables Cryptography Extensions.
489 @cindex @code{-mfpu=} command-line option, ARM
496 @code{softfpa},
497 @code{fpe},
498 @code{fpe2},
499 @code{fpe3},
500 @code{fpa},
501 @code{fpa10},
502 @code{fpa11},
503 @code{arm7500fe},
504 @code{softvfp},
505 @code{softvfp+vfp},
506 @code{vfp},
507 @code{vfp10},
508 @code{vfp10-r0},
509 @code{vfp9},
510 @code{vfpxd},
511 @code{vfpv2},
512 @code{vfpv3},
513 @code{vfpv3-fp16},
514 @code{vfpv3-d16},
515 @code{vfpv3-d16-fp16},
516 @code{vfpv3xd},
517 @code{vfpv3xd-d16},
518 @code{vfpv4},
519 @code{vfpv4-d16},
520 @code{fpv4-sp-d16},
521 @code{fpv5-sp-d16},
522 @code{fpv5-d16},
523 @code{fp-armv8},
524 @code{arm1020t},
525 @code{arm1020e},
526 @code{arm1136jf-s},
527 @code{maverick},
528 @code{neon},
529 @code{neon-vfpv3},
530 @code{neon-fp16},
531 @code{neon-vfpv4},
532 @code{neon-fp-armv8},
533 @code{crypto-neon-fp-armv8},
534 @code{neon-fp-armv8.1}
536 @code{crypto-neon-fp-armv8.1}.
539 also affects the way in which the @code{.double} assembler directive behaves
540 when assembling little-endian code.
546 @cindex @code{-mfp16-format=} command-line option
549 when assembling floating point numbers emitted by the @code{.float16}
552 @code{ieee},
553 @code{alternative}.
554 If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
555 point format is used, if @code{alternative} is specified then the Arm
558 the @code{float16_format} directive. If this value is not set then
560 the @code{float16_format} directive.
562 @cindex @code{-mthumb} command-line option, ARM
566 @code{.code 16} directive.
568 @cindex @code{-mthumb-interwork} command-line option, ARM
572 of the @code{ADR} and @code{ADRL} pseudo opcodes.
574 @cindex @code{-mimplicit-it} command-line option, ARM
579 The @code{-mimplicit-it} option controls the behavior of the assembler when
582 If @code{never} is specified, such constructs cause a warning in ARM
583 code and an error in Thumb-2 code.
584 If @code{always} is specified, such constructs are accepted in both
585 ARM and Thumb-2 code, where the IT instruction is added implicitly.
586 If @code{arm} is specified, such constructs are accepted in ARM code
587 and cause an error in Thumb-2 code.
588 If @code{thumb} is specified, such constructs cause a warning in ARM
589 code and are accepted in Thumb-2 code.  If you omit this option, the
590 behavior is equivalent to @code{-mimplicit-it=arm}.
592 @cindex @code{-mapcs-26} command-line option, ARM
593 @cindex @code{-mapcs-32} command-line option, ARM
600 @cindex @code{-matpcs} command-line option, ARM
608 @cindex @code{-mapcs-float} command-line option, ARM
614 @cindex @code{-mapcs-reentrant} command-line option, ARM
617 This variant supports position independent code.
619 @cindex @code{-mfloat-abi=} command-line option, ARM
624 @code{soft},
625 @code{softfp}
627 @code{hard}.
629 @cindex @code{-eabi=} command-line option, ARM
634 @code{gnu},
635 @code{4}
637 @code{5}.
639 @cindex @code{-EB} command-line option, ARM
646 @option{-EB} option, (all of it, code and data) and then linked with
650 @cindex @code{-EL} command-line option, ARM
655 @cindex @code{-k} command-line option, ARM
656 @cindex PIC code generation for ARM
659 as position-independent code (PIC).
661 @cindex @code{--fix-v4bx} command-line option, ARM
663 Allow @code{BX} instructions in ARMv4 code.  This is intended for use with
666 @cindex @code{-mwarn-deprecated} command-line option, ARM
672 @cindex @code{-mccs} command-line option, ARM
676 @cindex @code{-mwarn-syms} command-line option, ARM
698 instructions.  The default, @code{divided}, uses the old style where
700 @code{unified} syntax, which can be selected via the @code{.syntax}
705 Immediate operands do not require a @code{#} prefix.
708 The @code{IT} instruction may appear, and if it does it is validated
710 generate machine code, in THUMB mode it does.
715 used, but only inside the scope of an @code{IT} instruction.
720 @code{divided} syntax).
723 The @code{.N} and @code{.W} suffixes are recognized and honored.
726 All instructions set the flags if and only if they have an @code{s}
779 @code{GOT},
780 @code{GOTOFF},
781 @code{TARGET1},
782 @code{TARGET2},
783 @code{SBREL},
784 @code{TLSGD},
785 @code{TLSLDM},
786 @code{TLSLDO},
787 @code{TLSDESC},
788 @code{TLSCALL},
789 @code{GOTTPOFF},
790 @code{GOT_PREL}
792 @code{TPOFF}.
795 @code{(PLT)} after branch targets.  On legacy targets this will
853 @table @code
858 @cindex @code{.2byte} directive, ARM
859 @cindex @code{.4byte} directive, ARM
860 @cindex @code{.8byte} directive, ARM
867 @cindex @code{.align} directive, ARM
874 @cindex @code{.arch} directive, ARM
880 Specifying @code{.arch} clears any previously selected architecture
883 @cindex @code{.arch_extension} directive, ARM
889 @code{.arch_extension} may be used multiple times to add or remove extensions
892 @cindex @code{.arm} directive, ARM
894 This performs the same action as @var{.code 32}.
899 @cindex @code{.cantunwind} directive, ARM
904 @cindex @code{.code} directive, ARM
905 @item .code @code{[16|32]}
909 @cindex @code{.cpu} directive, ARM
915 Specifying @code{.cpu} clears any previously selected architecture
920 @cindex @code{.dn} and @code{.qn} directives, ARM
924 The @code{dn} and @code{qn} directives are used to create typed
947 Aliases created using @code{dn} or @code{qn} can be destroyed using
948 @code{unreq}.
952 @cindex @code{.eabi_attribute} directive, ARM
957 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
958 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
959 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
960 @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config},
961 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
962 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
963 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
964 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
965 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
966 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
967 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
968 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
969 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
970 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
971 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
972 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
973 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
974 @code{Tag_conformance}, @code{Tag_T2EE_use},
975 @code{Tag_Virtualization_use}
977 The @var{value} is either a @code{number}, @code{"string"}, or
978 @code{number, "string"} depending on the tag.
981 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
982 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
984 @cindex @code{.even} directive, ARM
988 @cindex @code{.extend} directive, ARM
989 @cindex @code{.ldouble} directive, ARM
998 @cindex @code{.float16} directive, ARM
1002 encoding is specified by @code{.float16_format}. If the format has not
1003 been explicitly set yet (either via the @code{.float16_format} directive or
1006 @cindex @code{.float16_format} directive, ARM
1009 the @code{.float16} directive.
1011 @code{format} should be one of the following: @code{ieee} (encode in
1012 the IEEE 754-2008 half precision format) or @code{alternative} (encode in
1016 @cindex @code{.fnend} directive, ARM
1026 @cindex @code{.fnstart} directive, ARM
1030 @cindex @code{.force_thumb} directive, ARM
1035 @cindex @code{.fpu} directive, ARM
1043 @cindex @code{.handlerdata} directive, ARM
1047 @code{.fnend} directive will be added to the exception table entry.
1049 Must be preceded by a @code{.personality} or @code{.personalityindex}
1054 @cindex @code{.inst} directive, ARM
1059 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
1067 See @code{.extend}.
1069 @cindex @code{.ltorg} directive, ARM
1074 @code{GAS} maintains a separate literal pool for each section and each
1075 sub-section.  The @code{.ltorg} directive will only affect the literal
1079 Note - older versions of @code{GAS} would dump the current literal
1085 @cindex @code{.movsp} directive, ARM
1094 @cindex @code{.object_arch} directive, ARM
1097 Valid values for @var{name} are the same as for the @code{.arch} directive.
1098 Typically this is useful when code uses runtime detection of CPU features.
1102 @cindex @code{.packed} directive, ARM
1109 @cindex @code{.pacspval} directive, ARM
1115 @cindex @code{.pad} directive, ARM
1121 @cindex @code{.personality} directive, ARM
1125 @cindex @code{.personalityindex} directive, ARM
1130 @cindex @code{.pool} directive, ARM
1137 @cindex @code{.req} directive, ARM
1149 @cindex @code{.save} directive, ARM
1177 @cindex @code{.setfp} directive, ARM
1182 The syntax of this directive is the same as the @code{add} or @code{mov}
1184 @code{sp} or mentioned in a previous @code{.movsp} directive.
1194 @cindex @code{.secrel32} directive, ARM
1200 @cindex @code{.syntax} directive, ARM
1201 @item .syntax [@code{unified} | @code{divided}]
1207 @cindex @code{.thumb} directive, ARM
1209 This performs the same action as @var{.code 16}.
1211 @cindex @code{.thumb_func} directive, ARM
1215 the assembler and linker to generate correct code for interworking
1218 directive also implies @code{.thumb}
1221 targets the encoding is implicit when generating Thumb code.
1223 @cindex @code{.thumb_set} directive, ARM
1225 This performs the equivalent of a @code{.set} directive in that it
1229 way that the @code{.thumb_func} directive does.
1231 @cindex @code{.tlsdescseq} directive, ARM
1239 @cindex @code{.unreq} directive, ARM
1242 @code{req}, @code{dn} or @code{qn} directives.  For example:
1253 @cindex @code{.unwind_raw} directive, ARM
1258 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1259 @code{.save @{r0@}}
1263 @cindex @code{.vsave} directive, ARM
1281 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1295 @code{@value{AS}} implements all the standard ARM opcodes.  It also
1299 @table @code
1301 @cindex @code{NOP} pseudo op, ARM
1310 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1322 @cindex @code{ADR reg,<label>} pseudo op, ARM
1345 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1377 @table @code
1379 @cindex @code{$a}
1381 At the start of a region of code containing ARM instructions.
1383 @cindex @code{$t}
1385 At the start of a region of code containing THUMB instructions.
1387 @cindex @code{$d}
1394 is no need to code them yourself.  Support for tagging symbols ($b,
1412 If you are writing functions in assembly code, and those functions
1416 code throws an exception, the run-time library will be unable to
1417 unwind the stack through your assembly code and your program will not
1420 To illustrate the use of these pseudo ops, we will examine the code
1436 assembly code.  That is a much more complex operation and should
1440 The code generated by one particular version of G++ when compiling the
1478 we assume that the assembly code does not itself throw an exception,
1480 as the @code{bl} instruction above.  At each call site, the same saved
1481 registers (including @code{lr}, which indicates the return address)
1484 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1486 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1490 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1491 @code{.pad}) matters; their exact locations are irrelevant.  In the
1493 instructions.  That makes it easier to understand the code, but it is
1495 of the pseudo ops other than @code{.fnend} in the same order, but
1496 immediately after @code{.fnstart}.
1498 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1501 @code{.save} pseudo op is a list of registers to save.  If a register
1503 function you are writing, then your code must save the value before it
1508 exception is not thrown, the function that contains the @code{.save}
1510 done with the @code{ldmfd} instruction above.)
1513 of the function and you do not need to use the @code{.save} pseudo op
1517 might throw an exception.  And, you must use the @code{.save} pseudo
1520 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1526 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1528 argument is the register that is set, which is typically @code{fp}.
1536 @code{.setfp} pseudo op.  If you do not use a frame pointer, then you
1542 code that calls functions which may throw exceptions.  If you need to