Lines Matching refs:MISC
418 {"standby", "%stdby_st", MISC (STANDBY), 4, ATTR_ALL, 0, NULL, 0, NULL},
419 {"mfsr", "=rt,%sr", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
420 {"iret", "", MISC (IRET), 4, ATTR_ALL, 0, NULL, 0, NULL},
421 {"trap", "%swid", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
422 {"teqz", "%rt{,%swid}", MISC (TEQZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
423 {"tnez", "%rt{,%swid}", MISC (TNEZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
424 {"dsb", "", MISC (DSB), 4, ATTR_ALL, 0, NULL, 0, NULL},
425 {"isb", "", MISC (ISB), 4, ATTR_ALL, 0, NULL, 0, NULL},
426 {"break", "%swid", MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL},
427 {"syscall", "%swid", MISC (SYSCALL), 4, ATTR_ALL, 0, NULL, 0, NULL},
428 {"msync", "%msync_st", MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
429 {"isync", "%rt", MISC (ISYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
431 {"mtsr", "%rt,%sr", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
433 …{"setend.l", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (5), 4, ATTR_ALL, 0, NULL, 0, NUL…
434 …{"setend.b", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (5) | N32_BIT (20), 4, ATTR_ALL, …
436 …{"setgie.d", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (6), 4, ATTR_ALL, 0, NULL, 0, NUL…
437 …{"setgie.e", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (6) | N32_BIT (20), 4, ATTR_ALL, …
438 {"mfsr", "=rt,%ridx", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
439 {"mtsr", "%rt,%ridx", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
440 {"trap", "", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
441 {"break", "", MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL},
442 {"msync", "", MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
444 {"tlbop", "%ra,%tlbop_st", MISC (TLBOP), 4, ATTR_ALL, 0, NULL, 0, NULL},
445 {"tlbop", "%ra,%tlbop_stx", MISC (TLBOP), 4, ATTR_ALL, 0, NULL, 0, NULL},
446 {"tlbop", "%rt,%ra,pb", MISC (TLBOP) | (5 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL},
447 {"tlbop", "%rt,%ra,probe", MISC (TLBOP) | (5 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL},
448 {"tlbop", "flua", MISC (TLBOP) | (7 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL},
449 {"tlbop", "flushall", MISC (TLBOP) | (7 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL},
635 {"cctl", "%ra,%cctl_st0", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
636 {"cctl", "%ra,%cctl_st1{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
637 {"cctl", "=rt,%ra,%cctl_st2", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
638 {"cctl", "%rt,%ra,%cctl_st3", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
639 {"cctl", "%cctl_st4", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
640 {"cctl", "%cctl_st5{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3, 0, NULL, 0, NULL},
641 {"cctl", "=rt,%ra,%cctl_stx,%cctl_lv", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
979 {"bpick", "=rt,%ra,%rb,%rd", MISC (BPICK), 4, ATTR (DSP_ISAEXT), 0, NULL, 0, NULL},