54       insert_field (kind, code, value, mask);  in insert_fields()
74 	insert_field (kind, code, value, 0);  in insert_all_fields()
99   insert_field (self->fields[0], code, info->reg.regno, 0);  in aarch64_ins_regno()
112   insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask);  in aarch64_ins_reglane()
123 	  insert_field (FLD_imm4, code, value, 0);  in aarch64_ins_reglane()
135 	  insert_field (FLD_imm5, code, value, 0);  in aarch64_ins_reglane()
158       insert_field (FLD_SM3_imm2, code, reglane_index, 0);  in aarch64_ins_reglane()
185 	  insert_field (FLD_H, code, reglane_index, 0);  in aarch64_ins_reglane()
202   insert_field (self->fields[0], code, info->reglist.first_regno, 0);  in aarch64_ins_reglist()
204   insert_field (FLD_len, code, info->reglist.num_regs - 1, 0);  in aarch64_ins_reglist()
221   insert_field (FLD_Rt, code, info->reglist.first_regno, 0);  in aarch64_ins_ldst_reglist()
247   insert_field (FLD_opcode, code, value, 0);  in aarch64_ins_ldst_reglist()
266   insert_field (FLD_Rt, code, info->reglist.first_regno, 0);  in aarch64_ins_ldst_reglist_r()
273   insert_field (FLD_S, code, value, 0);  in aarch64_ins_ldst_reglist_r()
293   insert_field (FLD_Rt, code, info->reglist.first_regno, 0);  in aarch64_ins_ldst_elemlist()
353       insert_field (FLD_Q, code, Q, inst->opcode->mask);  in aarch64_ins_advsimd_imm_shift()
412   insert_field (FLD_hw, code, info->shifter.amount >> 4, 0);  in aarch64_ins_imm_half()
496   insert_field (self->fields[0], code, rot, inst->opcode->mask);  in aarch64_ins_imm_rotate1()
509   insert_field (self->fields[0], code, rot, inst->opcode->mask);  in aarch64_ins_imm_rotate2()
521   insert_field (self->fields[0], code, 64 - info->imm.value, 0);  in aarch64_ins_fbits()
534   insert_field (self->fields[0], code, value, 0);  in aarch64_ins_aimm()
536   insert_field (self->fields[1], code, info->imm.value, 0);  in aarch64_ins_aimm()
610       insert_field (FLD_ldst_size, code, value, 0);  in aarch64_ins_ft()
630   insert_field (FLD_Rn, code, info->addr.base_regno, 0);  in aarch64_ins_addr_simple()
646   insert_field (FLD_Rn, code, info->addr.base_regno, 0);  in aarch64_ins_addr_regoff()
648   insert_field (FLD_Rm, code, info->addr.offset.regno, 0);  in aarch64_ins_addr_regoff()
652   insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);  in aarch64_ins_addr_regoff()
663   insert_field (FLD_S, code, S, 0);  in aarch64_ins_addr_regoff()
677   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ins_addr_offset()
681   insert_field (self->fields[1], code, imm, 0);  in aarch64_ins_addr_offset()
687       insert_field (self->fields[2], code, 1, 0);  in aarch64_ins_addr_offset()
703   insert_field (FLD_Rn, code, info->addr.base_regno, 0);  in aarch64_ins_addr_simm()
710   insert_field (self->fields[0], code, imm, 0);  in aarch64_ins_addr_simm()
720 	insert_field (self->fields[1], code, 1, 0);  in aarch64_ins_addr_simm()
737   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ins_addr_simm10()
740   insert_field (self->fields[1], code, imm >> 9, 0);  in aarch64_ins_addr_simm10()
741   insert_field (self->fields[2], code, imm, 0);  in aarch64_ins_addr_simm10()
746       insert_field (self->fields[3], code, 1, 0);  in aarch64_ins_addr_simm10()
762   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ins_addr_uimm12()
764   insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0);  in aarch64_ins_addr_uimm12()
777   insert_field (FLD_Rn, code, info->addr.base_regno, 0);  in aarch64_ins_simd_addr_post()
780     insert_field (FLD_Rm, code, info->addr.offset.regno, 0);  in aarch64_ins_simd_addr_post()
782     insert_field (FLD_Rm, code, 0x1f, 0);  in aarch64_ins_simd_addr_post()
794   insert_field (FLD_cond, code, info->cond->value, 0);  in aarch64_ins_cond()
854     insert_field (FLD_CRm, code, PSTATE_DECODE_CRM (info->sysreg.flags), 0);  in aarch64_ins_pstatefield()
880   insert_field (FLD_CRm, code, info->barrier->value, 0);  in aarch64_ins_barrier()
895   insert_field (FLD_CRm_dsb_nxs, code, value, 0);  in aarch64_ins_barrier_dsb_nxs()
909   insert_field (FLD_Rt, code, info->prfop->value, 0);  in aarch64_ins_prfop()
938   insert_field (FLD_Rm, code, info->reg.regno, 0);  in aarch64_ins_reg_extended()
944   insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);  in aarch64_ins_reg_extended()
946   insert_field (FLD_imm3, code, info->shifter.amount, 0);  in aarch64_ins_reg_extended()
960   insert_field (FLD_Rm, code, info->reg.regno, 0);  in aarch64_ins_reg_shifted()
962   insert_field (FLD_shift, code,  in aarch64_ins_reg_shifted()
965   insert_field (FLD_imm6, code, info->shifter.amount, 0);  in aarch64_ins_reg_shifted()
982   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ins_sve_addr_ri_s4xvl()
983   insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);  in aarch64_ins_sve_addr_ri_s4xvl()
999   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ins_sve_addr_ri_s6xvl()
1000   insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);  in aarch64_ins_sve_addr_ri_s6xvl()
1017   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ins_sve_addr_ri_s9xvl()
1033   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ins_sve_addr_ri_s4()
1034   insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);  in aarch64_ins_sve_addr_ri_s4()
1048   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ins_sve_addr_ri_u6()
1049   insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);  in aarch64_ins_sve_addr_ri_u6()
1062   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ins_sve_addr_rr_lsl()
1063   insert_field (self->fields[1], code, info->addr.offset.regno, 0);  in aarch64_ins_sve_addr_rr_lsl()
1077   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ins_sve_addr_rz_xtw()
1078   insert_field (self->fields[1], code, info->addr.offset.regno, 0);  in aarch64_ins_sve_addr_rz_xtw()
1080     insert_field (self->fields[2], code, 0, 0);  in aarch64_ins_sve_addr_rz_xtw()
1082     insert_field (self->fields[2], code, 1, 0);  in aarch64_ins_sve_addr_rz_xtw()
1096   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ins_sve_addr_zi_u5()
1097   insert_field (FLD_imm5, code, info->addr.offset.imm / factor, 0);  in aarch64_ins_sve_addr_zi_u5()
1110   insert_field (self->fields[0], code, info->addr.base_regno, 0);  in aarch64_ext_sve_addr_zz()
1111   insert_field (self->fields[1], code, info->addr.offset.regno, 0);  in aarch64_ext_sve_addr_zz()
1112   insert_field (FLD_SVE_msz, code, info->shifter.amount, 0);  in aarch64_ext_sve_addr_zz()
1191   insert_field (self->fields[0], code, info->reglane.regno, 0);  in aarch64_ins_sve_index()
1231   insert_field (self->fields[0], code, info->reglist.first_regno, 0);  in aarch64_ins_sve_reglist()
1245   insert_field (FLD_SVE_imm4, code, info->shifter.amount - 1, 0);  in aarch64_ins_sve_scale()
1294     insert_field (self->fields[0], code, 0, 0);  in aarch64_ins_sve_float_half_one()
1296     insert_field (self->fields[0], code, 1, 0);  in aarch64_ins_sve_float_half_one()
1310     insert_field (self->fields[0], code, 0, 0);  in aarch64_ins_sve_float_half_two()
1312     insert_field (self->fields[0], code, 1, 0);  in aarch64_ins_sve_float_half_two()
1326     insert_field (self->fields[0], code, 0, 0);  in aarch64_ins_sve_float_zero_one()
1328     insert_field (self->fields[0], code, 1, 0);  in aarch64_ins_sve_float_zero_one()
1378   insert_field (self->fields[0], code, fld_size, 0);  in aarch64_ins_sme_za_hv_tiles()
1379   insert_field (self->fields[1], code, fld_q, 0);  in aarch64_ins_sme_za_hv_tiles()
1380   insert_field (self->fields[2], code, fld_v, 0);  in aarch64_ins_sme_za_hv_tiles()
1381   insert_field (self->fields[3], code, fld_rv, 0);  in aarch64_ins_sme_za_hv_tiles()
1382   insert_field (self->fields[4], code, fld_zan_imm, 0);  in aarch64_ins_sme_za_hv_tiles()
1402   insert_field (self->fields[0], code, fld_mask, 0);  in aarch64_ins_sme_za_list()
1415   insert_field (self->fields[0], code, regno, 0);  in aarch64_ins_sme_za_array()
1416   insert_field (self->fields[1], code, imm, 0);  in aarch64_ins_sme_za_array()
1429   insert_field (self->fields[0], code, regno, 0);  in aarch64_ins_sme_addr_ri_u4xvl()
1430   insert_field (self->fields[1], code, imm, 0);  in aarch64_ins_sme_addr_ri_u4xvl()
1451   insert_field (self->fields[0], code, fld_crm, 0);  in aarch64_ins_sme_sm_za()
1472   insert_field (self->fields[0], code, fld_rm, 0);  in aarch64_ins_sme_pred_reg_with_index()
1473   insert_field (self->fields[1], code, fld_pn, 0);  in aarch64_ins_sme_pred_reg_with_index()
1516   insert_field (self->fields[2], code, fld_i1, 0);  in aarch64_ins_sme_pred_reg_with_index()
1517   insert_field (self->fields[3], code, fld_tszh, 0);  in aarch64_ins_sme_pred_reg_with_index()
1518   insert_field (self->fields[4], code, fld_tshl, 0);  in aarch64_ins_sme_pred_reg_with_index()
1531   insert_field (self->fields[0], code, info->reg.regno, 0);  in aarch64_ins_x0_to_x30()
1649       insert_field (FLD_SVE_Pm, &inst->value, value, 0);  in do_misc_encoding()
1650       insert_field (FLD_SVE_Pg4_10, &inst->value, value, 0);  in do_misc_encoding()
1655       insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);  in do_misc_encoding()
1665       insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);  in do_misc_encoding()
1672       insert_field (FLD_SVE_Pm, &inst->value, value, 0);  in do_misc_encoding()
1678       insert_field (FLD_SVE_Pm, &inst->value, value, 0);  in do_misc_encoding()
1684       insert_field (FLD_SVE_Pm, &inst->value, value, 0);  in do_misc_encoding()
1706   insert_field (FLD_Q, &inst->value, sizeq & 0x1, inst->opcode->mask);  in encode_sizeq()
1715   insert_field (kind, &inst->value, (sizeq >> 1) & 0x3, inst->opcode->mask);  in encode_sizeq()
1735       insert_field (FLD_cond2, &inst->value, inst->cond->value, 0);  in do_special_encoding()
1743       insert_field (FLD_sf, &inst->value, value, 0);  in do_special_encoding()
1745 	insert_field (FLD_N, &inst->value, value, inst->opcode->mask);  in do_special_encoding()
1753       insert_field (FLD_lse_sz, &inst->value, value, 0);  in do_special_encoding()
1767       insert_field (FLD_type, &inst->value, value, 0);  in do_special_encoding()
1777       insert_field (FLD_size, &inst->value, value, inst->opcode->mask);  in do_special_encoding()
1802       insert_field (FLD_Q, &inst->value, value & 0x1, inst->opcode->mask);  in do_special_encoding()
1822       insert_field (FLD_Q, &inst->value,  in do_special_encoding()
1885       insert_field (FLD_SVE_M_4, &inst->value, aarch64_get_variant (inst), 0);  in aarch64_encode_variant_using_iclass()
1890       insert_field (FLD_size, &inst->value, aarch64_get_variant (inst), 0);  in aarch64_encode_variant_using_iclass()
1894       insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) + 1, 0);  in aarch64_encode_variant_using_iclass()
1899       insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);  in aarch64_encode_variant_using_iclass()
1903       insert_field (FLD_SVE_sz2, &inst->value, aarch64_get_variant (inst), 0);  in aarch64_encode_variant_using_iclass()
1907       insert_field (FLD_SVE_size, &inst->value,  in aarch64_encode_variant_using_iclass()
1921       insert_field (FLD_size, &inst->value, variant, 0);  in aarch64_encode_variant_using_iclass()