Lines Matching refs:opcode
5 * opcode/pru.h: New file.
10 * opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
15 * opcode/mips.h: Replace `0' and `4' operand codes with `.' and
20 * opcode/mips.h (INSN2_SHORT_ONLY): New macro.
25 * opcode/xgate.h: Likewise.
29 * opcode/mips.h (mips_opcode_32bit_p): New inline function.
54 * opcode/aarch64.h (aarch64_operand_class): Remove
62 * opcode/mips.h: Remove references to `>' operand code.
66 * opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
70 * opcode/mips.h (ASE_DSPR3): Add a comment.
74 * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
79 * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
84 * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
90 * opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
111 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
117 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
122 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
126 * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
132 * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
138 * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
142 * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
150 * opcode/arc.h: Make macros 64-bit safe.
154 * opcode/arc.h (arc_opcode_len): Declare.
164 * opcode/riscv-opc.h: New file.
165 * opcode/riscv.h: New file.
194 * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
198 * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
202 * opcode/arc.h (insn_class_t): Add two new classes.
210 * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
214 * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
221 * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
228 * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
234 * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
240 * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
254 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
262 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
282 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
290 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
297 * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
302 * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
315 * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
320 * opcode/aarch64.h (F_STRICT): New flag.
324 * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
329 * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
339 * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
347 * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
350 * opcode/arc.h: Add BMU to insn_class_t enum.
351 * opcode/arc.h: Add PMU to insn_class_t enum.
373 * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
380 * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
385 * opcode/sparc.h (enum sparc_opcode_arch_val): Move
390 * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
409 * opcode/arc.h: Make insn_class_t alphabetical again.
415 * opcode/arc.h: Likewise.
419 * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
424 * opcode/arc.h: Add nps400 extension and instruction
431 * opcode/sparc.h (enum sparc_opcode_arch_val): Add
438 * opcode/msp430-decode.h (MSP430_Size): Remove.
447 * opcode/sparc.h: Add missing documentation for hyperprivileged
459 * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
465 * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
474 * opcode/d10v.h: Likewise.
475 * opcode/d30v.h: Likewise.
476 * opcode/ia64.h: Likewise.
477 * opcode/mips.h: Likewise.
478 * opcode/ppc.h: Likewise.
479 * opcode/sparc.h: Likewise.
480 * opcode/tic6x.h: Likewise.
481 * opcode/v850.h: Likewise.
492 * opcode/metag.h: wrap declarations in extern "C".
496 * opcode/arc.h (insn_subclass_t): Add COND.
501 * opcode/arc.h (struct arc_opcode): Renamed attribute class to
507 * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
519 * opcode/mips.h (ASE_DSPR3): New macro.
543 * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
550 * opcode/arc.h (ARC_SYNTAX_1OP): Declare
559 * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
580 * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
584 * opcode/arc.h (insn_class_t): Add NET and ACL class.
589 * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
593 * opcode/arc.h (flag_class_t): Update.
604 * opcode/arc.h (arc_num_opcodes): Remove.
621 * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
627 * opcode/arc-func.h (replace_bits24): Changed.
632 * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
649 * opcode/i960.h: Add const qualifiers.
650 * opcode/tic4x.h (struct tic4x_inst): Likewise.
658 * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
664 * opcode/arc.h (ARC_OPCODE_NPS400): Define.
677 * opcode/arc.h (ARC_OPCODE_BASE): Delete.
692 * opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
693 * opcode/h8300.h (struct h8_opcode): Likewise.
694 * opcode/hppa.h (struct pa_opcode): Likewise.
695 * opcode/msp430.h: Likewise.
696 * opcode/spu.h (struct spu_opcode): Likewise.
697 * opcode/tic30.h (struct _register): Likewise.
698 * opcode/tic4x.h (struct tic4x_register): Likewise.
702 * opcode/visium.h (struct reg_entry): Likewise.
740 * opcode/arm.h (ARM_EXT2_FP16_INSN): New.
745 * opcode/arc.h (arc_opcode arc_relax_opcodes)
750 * opcode/metag.h (metag_scondtab): Mark as possibly unused.
751 * opcode/nds32.h (nds32_r45map): Likewise.
753 * opcode/visium.h (gen_reg_table): Likewise.
764 * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
787 * opcode/arc-func.h: Changed all the replacement
814 * opcode/mips.h: Add a summary of MIPS16 operand codes.
827 mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,