Lines Matching refs:samp

58 @cindex @samp{--32} option, i386
59 @cindex @samp{--32} option, x86-64
60 @cindex @samp{--x32} option, i386
61 @cindex @samp{--x32} option, x86-64
62 @cindex @samp{--64} option, i386
63 @cindex @samp{--64} option, x86-64
65 Select the word size, either 32 bits or 64 bits.  @samp{--32}
66 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
85 @samp{--divide} option turns @samp{/} into a normal character.  This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
300 @cindex @samp{-mtune=} option, i386
301 @cindex @samp{-mtune=} option, x86-64
311 @cindex @samp{-msse2avx} option, i386
312 @cindex @samp{-msse2avx} option, x86-64
317 @cindex @samp{-muse-unaligned-vector-move} option, i386
318 @cindex @samp{-muse-unaligned-vector-move} option, x86-64
323 @cindex @samp{-msse-check=} option, i386
324 @cindex @samp{-msse-check=} option, x86-64
335 @cindex @samp{-mavxscalar=} option, i386
336 @cindex @samp{-mavxscalar=} option, x86-64
348 @cindex @samp{-mvexwig=} option, i386
349 @cindex @samp{-mvexwig=} option, x86-64
361 @cindex @samp{-mevexlig=} option, i386
362 @cindex @samp{-mevexlig=} option, x86-64
373 @cindex @samp{-mevexwig=} option, i386
374 @cindex @samp{-mevexwig=} option, x86-64
383 @cindex @samp{-mmnemonic=} option, i386
384 @cindex @samp{-mmnemonic=} option, x86-64
391 @cindex @samp{-msyntax=} option, i386
392 @cindex @samp{-msyntax=} option, x86-64
399 @cindex @samp{-mnaked-reg} option, i386
400 @cindex @samp{-mnaked-reg} option, x86-64
402 This option specifies that registers don't require a @samp{%} prefix.
405 @cindex @samp{-madd-bnd-prefix} option, i386
406 @cindex @samp{-madd-bnd-prefix} option, x86-64
411 @cindex @samp{-mshared} option, i386
412 @cindex @samp{-mshared} option, x86-64
416 The @samp{-mshared} option tells the assembler to generate code which
422 @cindex @samp{-mbig-obj} option, i386
423 @cindex @samp{-mbig-obj} option, x86-64
428 @cindex @samp{-momit-lock-prefix=} option, i386
429 @cindex @samp{-momit-lock-prefix=} option, x86-64
440 @cindex @samp{-mfence-as-lock-add=} option, i386
441 @cindex @samp{-mfence-as-lock-add=} option, x86-64
447 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
448 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
452 @cindex @samp{-mrelax-relocations=} option, i386
453 @cindex @samp{-mrelax-relocations=} option, x86-64
464 @cindex @samp{-malign-branch-boundary=} option, i386
465 @cindex @samp{-malign-branch-boundary=} option, x86-64
473 @cindex @samp{-malign-branch=} option, i386
474 @cindex @samp{-malign-branch=} option, x86-64
477 combination of @samp{jcc}, which aligns conditional jumps,
478 @samp{fused}, which aligns fused conditional jumps, @samp{jmp},
479 which aligns unconditional jumps, @samp{call} which aligns calls,
480 @samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect
483 @cindex @samp{-malign-branch-prefix-size=} option, i386
484 @cindex @samp{-malign-branch-prefix-size=} option, x86-64
490 @cindex @samp{-mbranches-within-32B-boundaries} option, i386
491 @cindex @samp{-mbranches-within-32B-boundaries} option, x86-64
501 @cindex @samp{-mlfence-after-load=} option, i386
502 @cindex @samp{-mlfence-after-load=} option, x86-64
510 @cindex @samp{-mlfence-before-indirect-branch=} option, i386
511 @cindex @samp{-mlfence-before-indirect-branch=} option, x86-64
533 @cindex @samp{-mlfence-before-ret=} option, i386
534 @cindex @samp{-mlfence-before-ret=} option, x86-64
548 @cindex @samp{-mx86-used-note=} option, i386
549 @cindex @samp{-mx86-used-note=} option, x86-64
557 @cindex @samp{-mevexrcig=} option, i386
558 @cindex @samp{-mevexrcig=} option, x86-64
570 @cindex @samp{-mamd64} option, x86-64
571 @cindex @samp{-mintel64} option, x86-64
578 @cindex @samp{-O0} option, i386
579 @cindex @samp{-O0} option, x86-64
580 @cindex @samp{-O} option, i386
581 @cindex @samp{-O} option, x86-64
582 @cindex @samp{-O1} option, i386
583 @cindex @samp{-O1} option, x86-64
584 @cindex @samp{-O2} option, i386
585 @cindex @samp{-O2} option, x86-64
586 @cindex @samp{-Os} option, i386
587 @cindex @samp{-Os} option, x86-64
589 Optimize instruction encoding with smaller instruction size.  @samp{-O}
590 and @samp{-O1} encode 64-bit register load instructions with 64-bit
600 @samp{-O2} includes @samp{-O1} optimization plus encodes
608 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
610 immediate.  @samp{-O0} turns off this optimization.
682 require a @samp{%} prefix.  AT&T System V/386 assembler syntax is quite
704 AT&T immediate operands are preceded by @samp{$}; Intel immediate
705 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
706 AT&T register operands are preceded by @samp{%}; Intel register operands
708 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
716 operands.  Intel @samp{add eax, 4} is @samp{addl $4, %eax}.  The
717 @samp{source, dest} convention is maintained for compatibility with
718 previous Unix assemblers.  Note that @samp{bound}, @samp{invlpga}, and
719 instructions with 2 immediate operands, such as the @samp{enter}
730 character of the instruction mnemonic.  Mnemonic suffixes of @samp{b},
731 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
733 of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
737 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
738 @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}.  Thus, Intel
739 syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
740 syntax.  In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
741 @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
743 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
752 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
754 @samp{call/jmp far @var{section}:@var{offset}}.  Also, the far return
756 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
757 @samp{ret far @var{stack-adjust}}.
773 The presence of a @samp{#} appearing anywhere on a line indicates the
776 If a @samp{#} appears as the first character of a line then the whole
782 then the @samp{/} character appearing anywhere on a line also
788 The @samp{;} character can be used to separate statements on the same
801 specify the size of operands.  The letters @samp{b}, @samp{w}, @samp{l}
802 and @samp{q} specify byte, word, long and quadruple word operands.  If
805 (the last one by convention).  Thus, @samp{mov %ax, %bx} is equivalent
806 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
807 @samp{movw $1, bx}.  Note that this is incompatible with the AT&T Unix
844 @samp{@{disp8@}} -- prefer 8-bit displacement.
847 @samp{@{disp32@}} -- prefer 32-bit displacement.
850 @samp{@{disp16@}} -- prefer 16-bit displacement.
853 @samp{@{load@}} -- prefer load-form instruction.
856 @samp{@{store@}} -- prefer store-form instruction.
859 @samp{@{vex@}} --  encode with VEX prefix.
862 @samp{@{vex3@}} -- encode with 3-byte VEX prefix.
865 @samp{@{evex@}} --  encode with EVEX prefix.
868 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
869 instructions (x86-64 only).  Note that this differs from the @samp{rex}
873 @samp{@{nooptimize@}} -- disable instruction size optimization.
877 by default.  The pseudo @samp{@{vex@}} prefix can be used to encode
888 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
891 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
894 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
897 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
900 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
904 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
905 @samp{%rdx:%rax} (x86-64 only),
909 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
910 @samp{cqto} in AT&T naming.  @code{@value{AS}} accepts either naming for these
921 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}.
924 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}.
927 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64}
931 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32}
934 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64}
938 @samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64}
942 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}.
945 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}.
948 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64}
952 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32}
955 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64}
960 are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx},
961 @samp{movsbq/movsxb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw},
962 @samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx},
963 @samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx},
964 @samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax.
970 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
971 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
983 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
984 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
985 @samp{fsubr} and @samp{fsubrp},  are implemented in AT&T System V/386
990 @item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination
991 register.  @samp{movsxd} should be used to encode 16-bit or 32-bit
1002 Register operands are always prefixed with @samp{%}.  The 80386 registers
1007 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
1008 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
1009 frame pointer), and @samp{%esp} (the stack pointer).
1012 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
1013 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
1016 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
1017 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
1018 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
1019 @samp{%cx}, and @samp{%dx})
1022 the 6 section registers @samp{%cs} (code section), @samp{%ds}
1023 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
1024 and @samp{%gs}.
1027 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
1028 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
1031 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
1032 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
1035 the 2 test registers @samp{%tr6} and @samp{%tr7}.
1038 the 8 floating point register stack @samp{%st} or equivalently
1039 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
1040 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
1041 These registers are overloaded by 8 MMX registers @samp{%mm0},
1042 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
1043 @samp{%mm6} and @samp{%mm7}.
1046 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
1047 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
1054 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
1055 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
1056 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
1060 the 8 extended registers @samp{%r8}--@samp{%r15}.
1063 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
1066 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
1069 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
1072 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
1075 the 8 debug registers: @samp{%db8}--@samp{%db15}.
1078 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
1086 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
1088 @samp{xmm0}--@samp{xmm15} registers.
1097 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
1099 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
1100 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
1103 the 8 mask registers @samp{%k0}--@samp{%k7}.
1119 they act upon. For example, the @samp{scas} (scan string) instruction is
1135 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
1136 @samp{fs}, @samp{gs}.  These are automatically added by specifying
1141 Operand/Address size prefixes @samp{data16} and @samp{addr16}
1143 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
1156 The bus lock prefix @samp{lock} inhibits interrupts during execution of
1162 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
1168 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
1169 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
1173 The @samp{rex} family of prefixes is used by x86-64 to encode
1174 extensions to i386 instruction set.  The @samp{rex} prefix has four
1179 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
1180 instruction emits @samp{rex} prefix with all the bits set.  By omitting
1216 be preceded by a @samp{%}.  If you specify a section override which
1225 @item AT&T: @samp{-4(%ebp)}, Intel:  @samp{[ebp - 4]}
1226 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1227 missing, and the default section is used (@samp{%ss} for addressing with
1228 @samp{%ebp} as the base register).  @var{index}, @var{scale} are both missing.
1230 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1231 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1232 @samp{foo}.  All other fields are missing.  The section register here
1233 defaults to @samp{%ds}.
1235 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1236 This uses the value pointed to by @samp{foo} as a memory operand.
1238 @emph{one} @samp{,}.  This is a syntactic exception.
1240 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1241 This selects the contents of the variable @samp{foo} with section
1242 register @var{section} being @samp{%gs}.
1246 prefixed with @samp{*}.  If no @samp{*} is specified, @code{@value{AS}}
1251 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1255 addressing.  This addressing mode is specified by using @samp{rip} as a
1259 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1263 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1283 instruction with the @samp{data16} instruction prefix), since the 80386
1284 insists upon masking @samp{%eip} to 16 bits after the word displacement
1287 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1288 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1291 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1330 Floating point constructors are @samp{.float} or @samp{.single},
1331 @samp{.double}, @samp{.tfloat}, @samp{.hfloat}, and @samp{.bfloat16} for 32-,
1333 correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, and @samp{t}.
1334 @samp{t} stands for 80-bit (ten byte) real.  The 80387 only supports this
1335 format via the @samp{fldt} (load 80-bit real to stack top) and @samp{fstpt}
1347 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1348 @samp{.quad} for the 16-, 32-, and 64-bit integer formats.  The
1349 corresponding instruction mnemonic suffixes are @samp{s} (short),
1350 @samp{l} (long), and @samp{q} (quad).  As with the 80-bit real format,
1351 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1352 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1357 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1358 wrote @samp{fst %st, %st(1)}, since all register to register operations
1359 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1360 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1361 then stores the result in the 4 byte location @samp{mem})
1383 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1384 @samp{%mm1}, ... @samp{%mm7}.  They contain eight 8-bit integers, four
1455 mode code segments.  To do this, put a @samp{.code16} or
1456 @samp{.code16gcc} directive before the assembly language instructions to
1458 32-bit code with the @samp{.code32} directive or 64-bit code with the
1459 @samp{.code64} directive.
1461 @samp{.code16gcc} provides experimental support for generating 16-bit
1462 code from gcc, and differs from @samp{.code16} in that @samp{call},
1463 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1464 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1468 @samp{.code16gcc} also automatically adds address size prefixes where
1481 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1482 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1489 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1507 @item @samp{default} @tab @samp{push} @tab @samp{pop}
1508 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1509 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1510 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1511 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1512 @item @samp{corei7} @tab @samp{iamcu}
1513 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1514 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1515 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
1516 @item @samp{btver1} @tab @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
1517 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1518 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
1519 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1520 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1521 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1522 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1523 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1524 @item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
1525 @item @samp{.hle}
1526 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1527 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1528 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1529 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1530 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1531 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1532 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1533 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1534 @item @samp{.tdx} @tab @samp{.avx_vnni}  @tab @samp{.avx512_fp16}
1535 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
1536 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1537 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1538 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
1539 @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_tile}
1540 @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
1541 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1542 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
1543 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1544 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
1545 @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
1546 @item @samp{.tlbsync}
1551 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1555 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1556 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1557 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1563 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1564 control automatic promotion of conditional jumps. @samp{jumps} is the
1567 (@pxref{i386-Jumps})  @samp{nojumps} leaves external conditional jumps as
1570 Unconditional jumps are treated as for @samp{jumps}.
1584 @item For @samp{movsxd} with 16-bit destination register, AMD64
1590 operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax
1591 and with an explicit @samp{tbyte ptr} operand size specifier in Intel
1594 @item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16-
1616 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1617 than the expected @samp{%st(3) - %st}.  This happens with all the
1619 operands where the source register is @samp{%st} and the destination
1620 register is @samp{%st(i)}.
1630 There is some trickery concerning the @samp{mul} and @samp{imul}
1632 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1633 for @samp{imul}) can be output only in the one operand form.  Thus,
1634 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1635 the expanding multiply would clobber the @samp{%edx} register, and this
1636 would confuse @code{@value{GCC}} output.  Use @samp{imul %ebx} to get the
1637 64-bit product in @samp{%edx:%eax}.
1639 We have added a two operand form of @samp{imul} when the first operand
1641 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1642 example, can be done with @samp{imul $69, %eax} rather than @samp{imul