Lines Matching refs:code

33 @table @code
35 @cindex @code{-mcpu=} command-line option, ARM
41 @code{arm1},
42 @code{arm2},
43 @code{arm250},
44 @code{arm3},
45 @code{arm6},
46 @code{arm60},
47 @code{arm600},
48 @code{arm610},
49 @code{arm620},
50 @code{arm7},
51 @code{arm7m},
52 @code{arm7d},
53 @code{arm7dm},
54 @code{arm7di},
55 @code{arm7dmi},
56 @code{arm70},
57 @code{arm700},
58 @code{arm700i},
59 @code{arm710},
60 @code{arm710t},
61 @code{arm720},
62 @code{arm720t},
63 @code{arm740t},
64 @code{arm710c},
65 @code{arm7100},
66 @code{arm7500},
67 @code{arm7500fe},
68 @code{arm7t},
69 @code{arm7tdmi},
70 @code{arm7tdmi-s},
71 @code{arm8},
72 @code{arm810},
73 @code{strongarm},
74 @code{strongarm1},
75 @code{strongarm110},
76 @code{strongarm1100},
77 @code{strongarm1110},
78 @code{arm9},
79 @code{arm920},
80 @code{arm920t},
81 @code{arm922t},
82 @code{arm940t},
83 @code{arm9tdmi},
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
86 @code{arm9e},
87 @code{arm926e},
88 @code{arm926ej-s},
89 @code{arm946e-r0},
90 @code{arm946e},
91 @code{arm946e-s},
92 @code{arm966e-r0},
93 @code{arm966e},
94 @code{arm966e-s},
95 @code{arm968e-s},
96 @code{arm10t},
97 @code{arm10tdmi},
98 @code{arm10e},
99 @code{arm1020},
100 @code{arm1020t},
101 @code{arm1020e},
102 @code{arm1022e},
103 @code{arm1026ej-s},
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
109 @code{arm1136j-s},
110 @code{arm1136jf-s},
111 @code{arm1156t2-s},
112 @code{arm1156t2f-s},
113 @code{arm1176jz-s},
114 @code{arm1176jzf-s},
115 @code{mpcore},
116 @code{mpcorenovfp},
117 @code{cortex-a5},
118 @code{cortex-a7},
119 @code{cortex-a8},
120 @code{cortex-a9},
121 @code{cortex-a15},
122 @code{cortex-a17},
123 @code{cortex-a32},
124 @code{cortex-a35},
125 @code{cortex-a53},
126 @code{cortex-a55},
127 @code{cortex-a57},
128 @code{cortex-a72},
129 @code{cortex-a73},
130 @code{cortex-a75},
131 @code{cortex-a76},
132 @code{cortex-a76ae},
133 @code{cortex-a77},
134 @code{cortex-a78},
135 @code{cortex-a78ae},
136 @code{cortex-a78c},
137 @code{cortex-a710},
138 @code{ares},
139 @code{cortex-r4},
140 @code{cortex-r4f},
141 @code{cortex-r5},
142 @code{cortex-r7},
143 @code{cortex-r8},
144 @code{cortex-r52},
145 @code{cortex-r52plus},
146 @code{cortex-m35p},
147 @code{cortex-m33},
148 @code{cortex-m23},
149 @code{cortex-m7},
150 @code{cortex-m4},
151 @code{cortex-m3},
152 @code{cortex-m1},
153 @code{cortex-m0},
154 @code{cortex-m0plus},
155 @code{cortex-x1},
156 @code{exynos-m1},
157 @code{marvell-pj4},
158 @code{marvell-whitney},
159 @code{neoverse-n1},
160 @code{neoverse-n2},
161 @code{neoverse-v1},
162 @code{xgene1},
163 @code{xgene2},
164 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
165 @code{i80200} (Intel XScale processor)
166 @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
168 @code{xscale}.
169 The special name @code{all} may be used to allow the
174 co-processor instruction space.  For example, @code{-mcpu=arm920+maverick}
175 is equivalent to specifying @code{-mcpu=ep9312}.
177 Multiple extensions may be specified, separated by a @code{+}.  The
184 This is done be prepending @code{no} to the option that adds the extension.
187 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
191 @code{bf16} (BFloat16 extensions for v8.6-A architecture),
192 @code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture),
193 @code{crc}
194 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
195 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
196 @code{fp} (Floating Point Extensions for v8-A architecture),
197 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
198 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, impl…
199 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
200 @code{iwmmxt},
201 @code{iwmmxt2},
202 @code{xscale},
203 @code{maverick},
204 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
206 @code{os} (Operating System for v6M architecture),
207 @code{predres} (Execution and Data Prediction Restriction Instruction for
209 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
211 @code{sec} (Security Extensions for v6K and v7-A architectures),
212 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
213 @code{virt} (Virtualization Extensions for v7-A architecture, implies
214 @code{idiv}),
215 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
216 @code{ras} (Reliability, Availability and Serviceability extensions
218 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
219 @code{simd})
221 @code{xscale}.
223 @cindex @code{-march=} command-line option, ARM
229 @code{armv1},
230 @code{armv2},
231 @code{armv2a},
232 @code{armv2s},
233 @code{armv3},
234 @code{armv3m},
235 @code{armv4},
236 @code{armv4xm},
237 @code{armv4t},
238 @code{armv4txm},
239 @code{armv5},
240 @code{armv5t},
241 @code{armv5txm},
242 @code{armv5te},
243 @code{armv5texp},
244 @code{armv6},
245 @code{armv6j},
246 @code{armv6k},
247 @code{armv6z},
248 @code{armv6kz},
249 @code{armv6-m},
250 @code{armv6s-m},
251 @code{armv7},
252 @code{armv7-a},
253 @code{armv7ve},
254 @code{armv7-r},
255 @code{armv7-m},
256 @code{armv7e-m},
257 @code{armv8-a},
258 @code{armv8.1-a},
259 @code{armv8.2-a},
260 @code{armv8.3-a},
261 @code{armv8-r},
262 @code{armv8.4-a},
263 @code{armv8.5-a},
264 @code{armv8-m.base},
265 @code{armv8-m.main},
266 @code{armv8.1-m.main},
267 @code{armv8.6-a},
268 @code{armv8.7-a},
269 @code{armv8.8-a},
270 @code{armv9-a},
271 @code{iwmmxt},
272 @code{iwmmxt2}
274 @code{xscale}.
275 If both @code{-mcpu} and
276 @code{-march} are specified, the assembler will use
277 the setting for @code{-mcpu}.
282 @code{-mfpu} option, the union of both feature enablement is taken.
285 …code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @cod…
287 @code{+fp}: Enables VFPv2 instructions.
288 @code{+nofp}: Disables all FPU instrunctions.
290 For @code{armv7}:
292 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
293 @code{+nofp}: Disables all FPU instructions.
295 For @code{armv7-a}:
297 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
298 @code{+vfpv3-d16}: Alias for @code{+fp}.
299 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
300 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
302 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
304 @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
305 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
306 @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
308 @code{+neon}: Alias for @code{+simd}.
309 @code{+neon-vfpv3}: Alias for @code{+simd}.
310 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
312 @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
314 @code{+mp}: Enables Multiprocessing Extensions.
315 @code{+sec}: Enables Security Extensions.
316 @code{+nofp}: Disables all FPU and NEON instructions.
317 @code{+nosimd}: Disables all NEON instructions.
319 For @code{armv7ve}:
321 @code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
322 @code{+vfpv4-d16}: Alias for @code{+fp}.
323 @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
324 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
325 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
327 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
329 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
330 @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
332 @code{+neon-vfpv4}: Alias for @code{+simd}.
333 @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
335 @code{+neon-vfpv3}: Alias for @code{+neon}.
336 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
339 @code{+nofp}: Disables all FPU and NEON instructions.
340 @code{+nosimd}: Disables all NEON instructions.
342 For @code{armv7-r}:
344 @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
346 @code{+vfpv3xd}: Alias for @code{+fp.sp}.
347 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
348 @code{+vfpv3-d16}: Alias for @code{+fp}.
349 @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
351 @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
353 @code{+idiv}: Enables integer division instructions in ARM mode.
354 @code{+nofp}: Disables all FPU instructions.
356 For @code{armv7e-m}:
358 @code{+fp}: Enables single-precision only VFPv4 instructions with 16
360 @code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
361 @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
363 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
364 @code{+fpv5-d16"}: Alias for @code{+fp.dp}.
365 @code{+nofp}: Disables all FPU instructions.
367 For @code{armv8-m.main}:
369 @code{+dsp}: Enables DSP Extension.
370 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
372 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
373 @code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0),
374 @code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1),
375 @code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2),
376 @code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3),
377 @code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4),
378 @code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5),
379 @code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6),
380 @code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7),
381 @code{+nofp}: Disables all FPU instructions.
382 @code{+nodsp}: Disables DSP Extension.
384 For @code{armv8.1-m.main}:
386 @code{+dsp}: Enables DSP Extension.
387 @code{+fp}: Enables single and half precision scalar Floating Point Extensions
389 @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
390 Armv8.1-M Mainline, implies @code{+fp}.
391 @code{+mve}: Enables integer only M-profile Vector Extension for
392 Armv8.1-M Mainline, implies @code{+dsp}.
393 @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for
394 Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}.
395 @code{+nofp}: Disables all FPU instructions.
396 @code{+nodsp}: Disables DSP Extension.
397 @code{+nomve}: Disables all M-profile Vector Extensions.
399 For @code{armv8-a}:
401 @code{+crc}: Enables CRC32 Extension.
402 @code{+simd}: Enables VFP and NEON for Armv8-A.
403 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
404 @code{+simd}.
405 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
406 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
408 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
409 @code{+nocrypto}: Disables Cryptography Extensions.
411 For @code{armv8.1-a}:
413 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
414 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
415 @code{+simd}.
416 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
417 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
419 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
420 @code{+nocrypto}: Disables Cryptography Extensions.
422 For @code{armv8.2-a} and @code{armv8.3-a}:
424 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
425 @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
426 @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
427 for Armv8.2-A, implies @code{+fp16}.
428 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
429 @code{+simd}.
430 @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
431 @code{+simd}.
432 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
433 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
435 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
436 @code{+nocrypto}: Disables Cryptography Extensions.
438 For @code{armv8.4-a}:
440 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
442 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
443 Variant Extensions for Armv8.2-A, implies @code{+simd}.
444 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
445 @code{+simd}.
446 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
447 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
449 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
450 @code{+nocryptp}: Disables Cryptography Extensions.
452 For @code{armv8.5-a}:
454 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
456 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
457 Variant Extensions for Armv8.2-A, implies @code{+simd}.
458 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
459 @code{+simd}.
460 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
461 @code{+nocryptp}: Disables Cryptography Extensions.
464 @cindex @code{-mfpu=} command-line option, ARM
471 @code{softfpa},
472 @code{fpe},
473 @code{fpe2},
474 @code{fpe3},
475 @code{fpa},
476 @code{fpa10},
477 @code{fpa11},
478 @code{arm7500fe},
479 @code{softvfp},
480 @code{softvfp+vfp},
481 @code{vfp},
482 @code{vfp10},
483 @code{vfp10-r0},
484 @code{vfp9},
485 @code{vfpxd},
486 @code{vfpv2},
487 @code{vfpv3},
488 @code{vfpv3-fp16},
489 @code{vfpv3-d16},
490 @code{vfpv3-d16-fp16},
491 @code{vfpv3xd},
492 @code{vfpv3xd-d16},
493 @code{vfpv4},
494 @code{vfpv4-d16},
495 @code{fpv4-sp-d16},
496 @code{fpv5-sp-d16},
497 @code{fpv5-d16},
498 @code{fp-armv8},
499 @code{arm1020t},
500 @code{arm1020e},
501 @code{arm1136jf-s},
502 @code{maverick},
503 @code{neon},
504 @code{neon-vfpv3},
505 @code{neon-fp16},
506 @code{neon-vfpv4},
507 @code{neon-fp-armv8},
508 @code{crypto-neon-fp-armv8},
509 @code{neon-fp-armv8.1}
511 @code{crypto-neon-fp-armv8.1}.
514 also affects the way in which the @code{.double} assembler directive behaves
515 when assembling little-endian code.
521 @cindex @code{-mfp16-format=} command-line option
524 when assembling floating point numbers emitted by the @code{.float16}
527 @code{ieee},
528 @code{alternative}.
529 If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
530 point format is used, if @code{alternative} is specified then the Arm
533 the @code{float16_format} directive. If this value is not set then
535 the @code{float16_format} directive.
537 @cindex @code{-mthumb} command-line option, ARM
541 @code{.code 16} directive.
543 @cindex @code{-mthumb-interwork} command-line option, ARM
547 of the @code{ADR} and @code{ADRL} pseudo opcodes.
549 @cindex @code{-mimplicit-it} command-line option, ARM
554 The @code{-mimplicit-it} option controls the behavior of the assembler when
557 If @code{never} is specified, such constructs cause a warning in ARM
558 code and an error in Thumb-2 code.
559 If @code{always} is specified, such constructs are accepted in both
560 ARM and Thumb-2 code, where the IT instruction is added implicitly.
561 If @code{arm} is specified, such constructs are accepted in ARM code
562 and cause an error in Thumb-2 code.
563 If @code{thumb} is specified, such constructs cause a warning in ARM
564 code and are accepted in Thumb-2 code.  If you omit this option, the
565 behavior is equivalent to @code{-mimplicit-it=arm}.
567 @cindex @code{-mapcs-26} command-line option, ARM
568 @cindex @code{-mapcs-32} command-line option, ARM
575 @cindex @code{-matpcs} command-line option, ARM
583 @cindex @code{-mapcs-float} command-line option, ARM
589 @cindex @code{-mapcs-reentrant} command-line option, ARM
592 This variant supports position independent code.
594 @cindex @code{-mfloat-abi=} command-line option, ARM
599 @code{soft},
600 @code{softfp}
602 @code{hard}.
604 @cindex @code{-eabi=} command-line option, ARM
609 @code{gnu},
610 @code{4}
612 @code{5}.
614 @cindex @code{-EB} command-line option, ARM
621 @option{-EB} option, (all of it, code and data) and then linked with
625 @cindex @code{-EL} command-line option, ARM
630 @cindex @code{-k} command-line option, ARM
631 @cindex PIC code generation for ARM
634 as position-independent code (PIC).
636 @cindex @code{--fix-v4bx} command-line option, ARM
638 Allow @code{BX} instructions in ARMv4 code.  This is intended for use with
641 @cindex @code{-mwarn-deprecated} command-line option, ARM
647 @cindex @code{-mccs} command-line option, ARM
651 @cindex @code{-mwarn-syms} command-line option, ARM
673 instructions.  The default, @code{divided}, uses the old style where
675 @code{unified} syntax, which can be selected via the @code{.syntax}
680 Immediate operands do not require a @code{#} prefix.
683 The @code{IT} instruction may appear, and if it does it is validated
685 generate machine code, in THUMB mode it does.
690 used, but only inside the scope of an @code{IT} instruction.
695 @code{divided} syntax).
698 The @code{.N} and @code{.W} suffixes are recognized and honored.
701 All instructions set the flags if and only if they have an @code{s}
754 @code{GOT},
755 @code{GOTOFF},
756 @code{TARGET1},
757 @code{TARGET2},
758 @code{SBREL},
759 @code{TLSGD},
760 @code{TLSLDM},
761 @code{TLSLDO},
762 @code{TLSDESC},
763 @code{TLSCALL},
764 @code{GOTTPOFF},
765 @code{GOT_PREL}
767 @code{TPOFF}.
770 @code{(PLT)} after branch targets.  On legacy targets this will
828 @table @code
833 @cindex @code{.2byte} directive, ARM
834 @cindex @code{.4byte} directive, ARM
835 @cindex @code{.8byte} directive, ARM
842 @cindex @code{.align} directive, ARM
849 @cindex @code{.arch} directive, ARM
855 Specifying @code{.arch} clears any previously selected architecture
858 @cindex @code{.arch_extension} directive, ARM
864 @code{.arch_extension} may be used multiple times to add or remove extensions
867 @cindex @code{.arm} directive, ARM
869 This performs the same action as @var{.code 32}.
873 @cindex @code{.bss} directive, ARM
875 This directive switches to the @code{.bss} section.
879 @cindex @code{.cantunwind} directive, ARM
884 @cindex @code{.code} directive, ARM
885 @item .code @code{[16|32]}
889 @cindex @code{.cpu} directive, ARM
895 Specifying @code{.cpu} clears any previously selected architecture
900 @cindex @code{.dn} and @code{.qn} directives, ARM
904 The @code{dn} and @code{qn} directives are used to create typed
927 Aliases created using @code{dn} or @code{qn} can be destroyed using
928 @code{unreq}.
932 @cindex @code{.eabi_attribute} directive, ARM
937 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
938 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
939 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
940 @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config},
941 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
942 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
943 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
944 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
945 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
946 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
947 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
948 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
949 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
950 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
951 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
952 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
953 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
954 @code{Tag_conformance}, @code{Tag_T2EE_use},
955 @code{Tag_Virtualization_use}
957 The @var{value} is either a @code{number}, @code{"string"}, or
958 @code{number, "string"} depending on the tag.
961 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
962 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
964 @cindex @code{.even} directive, ARM
968 @cindex @code{.extend} directive, ARM
969 @cindex @code{.ldouble} directive, ARM
978 @cindex @code{.float16} directive, ARM
982 encoding is specified by @code{.float16_format}. If the format has not
983 been explicitly set yet (either via the @code{.float16_format} directive or
986 @cindex @code{.float16_format} directive, ARM
989 the @code{.float16} directive.
991 @code{format} should be one of the following: @code{ieee} (encode in
992 the IEEE 754-2008 half precision format) or @code{alternative} (encode in
996 @cindex @code{.fnend} directive, ARM
1006 @cindex @code{.fnstart} directive, ARM
1010 @cindex @code{.force_thumb} directive, ARM
1015 @cindex @code{.fpu} directive, ARM
1023 @cindex @code{.handlerdata} directive, ARM
1027 @code{.fnend} directive will be added to the exception table entry.
1029 Must be preceded by a @code{.personality} or @code{.personalityindex}
1034 @cindex @code{.inst} directive, ARM
1039 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
1047 See @code{.extend}.
1049 @cindex @code{.ltorg} directive, ARM
1054 @code{GAS} maintains a separate literal pool for each section and each
1055 sub-section.  The @code{.ltorg} directive will only affect the literal
1059 Note - older versions of @code{GAS} would dump the current literal
1065 @cindex @code{.movsp} directive, ARM
1074 @cindex @code{.object_arch} directive, ARM
1077 Valid values for @var{name} are the same as for the @code{.arch} directive.
1078 Typically this is useful when code uses runtime detection of CPU features.
1082 @cindex @code{.packed} directive, ARM
1089 @cindex @code{.pad} directive, ARM
1095 @cindex @code{.personality} directive, ARM
1099 @cindex @code{.personalityindex} directive, ARM
1104 @cindex @code{.pool} directive, ARM
1111 @cindex @code{.req} directive, ARM
1123 @cindex @code{.save} directive, ARM
1151 @cindex @code{.setfp} directive, ARM
1156 The syntax of this directive is the same as the @code{add} or @code{mov}
1158 @code{sp} or mentioned in a previous @code{.movsp} directive.
1168 @cindex @code{.secrel32} directive, ARM
1174 @cindex @code{.syntax} directive, ARM
1175 @item .syntax [@code{unified} | @code{divided}]
1181 @cindex @code{.thumb} directive, ARM
1183 This performs the same action as @var{.code 16}.
1185 @cindex @code{.thumb_func} directive, ARM
1189 the assembler and linker to generate correct code for interworking
1192 directive also implies @code{.thumb}
1195 targets the encoding is implicit when generating Thumb code.
1197 @cindex @code{.thumb_set} directive, ARM
1199 This performs the equivalent of a @code{.set} directive in that it
1203 way that the @code{.thumb_func} directive does.
1205 @cindex @code{.tlsdescseq} directive, ARM
1213 @cindex @code{.unreq} directive, ARM
1216 @code{req}, @code{dn} or @code{qn} directives.  For example:
1227 @cindex @code{.unwind_raw} directive, ARM
1232 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1233 @code{.save @{r0@}}
1237 @cindex @code{.vsave} directive, ARM
1255 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1269 @code{@value{AS}} implements all the standard ARM opcodes.  It also
1273 @table @code
1275 @cindex @code{NOP} pseudo op, ARM
1284 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1296 @cindex @code{ADR reg,<label>} pseudo op, ARM
1319 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1351 @table @code
1353 @cindex @code{$a}
1355 At the start of a region of code containing ARM instructions.
1357 @cindex @code{$t}
1359 At the start of a region of code containing THUMB instructions.
1361 @cindex @code{$d}
1368 is no need to code them yourself.  Support for tagging symbols ($b,
1386 If you are writing functions in assembly code, and those functions
1390 code throws an exception, the run-time library will be unable to
1391 unwind the stack through your assembly code and your program will not
1394 To illustrate the use of these pseudo ops, we will examine the code
1410 assembly code.  That is a much more complex operation and should
1414 The code generated by one particular version of G++ when compiling the
1452 we assume that the assembly code does not itself throw an exception,
1454 as the @code{bl} instruction above.  At each call site, the same saved
1455 registers (including @code{lr}, which indicates the return address)
1458 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1460 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1464 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1465 @code{.pad}) matters; their exact locations are irrelevant.  In the
1467 instructions.  That makes it easier to understand the code, but it is
1469 of the pseudo ops other than @code{.fnend} in the same order, but
1470 immediately after @code{.fnstart}.
1472 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1475 @code{.save} pseudo op is a list of registers to save.  If a register
1477 function you are writing, then your code must save the value before it
1482 exception is not thrown, the function that contains the @code{.save}
1484 done with the @code{ldmfd} instruction above.)
1487 of the function and you do not need to use the @code{.save} pseudo op
1491 might throw an exception.  And, you must use the @code{.save} pseudo
1494 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1500 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1502 argument is the register that is set, which is typically @code{fp}.
1510 @code{.setfp} pseudo op.  If you do not use a frame pointer, then you
1516 code that calls functions which may throw exceptions.  If you need to