Lines Matching refs:constraint
8264 #define constraint(expr, err) \ macro
8321 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16), in do_scalar_fp16_v82_encode()
8490 constraint (!inst.operands[i].isreg, in encode_arm_addr_mode_common()
8540 constraint ((inst.operands[i].imm == REG_PC in encode_arm_addr_mode_2()
8567 constraint ((is_t || inst.operands[i].writeback), in encode_arm_addr_mode_2()
8605 constraint ((inst.operands[i].imm == REG_PC in encode_arm_addr_mode_3()
8608 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback, in encode_arm_addr_mode_3()
8616 constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel in encode_arm_addr_mode_3()
9269 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, in do_rd_rm_rn()
9297 constraint ((inst.operands[2].reg == REG_PC), BAD_PC); in do_rm_rd_rn()
9298 constraint (((inst.relocs[0].exp.X_op != O_constant in do_rm_rd_rn()
9374 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC in do_arit()
9397 constraint (msb > 32, _("bit-field extends past end of register")); in do_bfc()
9416 constraint (msb > 32, _("bit-field extends past end of register")); in do_bfi()
9428 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, in do_bfx()
9457 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 in encode_branch()
9522 constraint (inst.cond != COND_ALWAYS, BAD_COND); in do_blx()
9650 constraint (Rd == REG_SP, BAD_SP); in do_co_reg()
9656 constraint (Rd == REG_PC, BAD_PC); in do_co_reg()
9713 constraint (Rd == REG_PC, BAD_PC); in do_co_reg2c()
9714 constraint (Rn == REG_PC, BAD_PC); in do_co_reg2c()
9722 constraint (Rd == Rn, BAD_OVERLAP); in do_co_reg2c()
9759 constraint ((Rd == REG_PC), BAD_PC); in do_div()
9760 constraint ((Rn == REG_PC), BAD_PC); in do_div()
9761 constraint ((Rm == REG_PC), BAD_PC); in do_div()
9865 constraint (inst.operands[0].reg % 2 != 0, in do_ldrd()
9867 constraint (inst.operands[1].present in do_ldrd()
9870 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); in do_ldrd()
9871 constraint (!inst.operands[2].isreg, _("'[' expected")); in do_ldrd()
9901 constraint (!inst.operands[1].isreg || !inst.operands[1].preind in do_ldrex()
9919 constraint (inst.relocs[0].exp.X_op != O_constant in do_ldrex()
9923 constraint ((inst.operands[1].reg == REG_PC), BAD_PC); in do_ldrex()
9933 constraint (inst.operands[0].reg % 2 != 0, in do_ldrexd()
9935 constraint (inst.operands[1].present in do_ldrexd()
9940 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); in do_ldrexd()
9951 constraint (!(inst.operands[1].immisreg) in check_ldr_r15_aligned()
9976 constraint (inst.relocs[0].exp.X_op != O_constant in do_ldstt()
9993 constraint (inst.operands[0].reg == REG_PC, BAD_PC); in do_ldstv4()
10008 constraint (inst.relocs[0].exp.X_op != O_constant in do_ldsttv4()
10048 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC in do_mov()
10063 constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW, in do_mov16()
10065 constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT, in do_mov16()
10122 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), in do_vmrs()
10128 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) in do_vmrs()
10135 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main), in do_vmrs()
10142 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main) in do_vmrs()
10185 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), in do_vmsr()
10191 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) in do_vmsr()
10198 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main), in do_vmsr()
10205 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main) in do_vmsr()
10232 constraint (inst.operands[0].reg == REG_PC, BAD_PC); in do_mrs()
10244 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) in do_mrs()
10277 constraint (inst.operands[2].reg == REG_PC, BAD_PC); in do_mul()
10377 constraint (!inst.operands[0].isreg, in do_pld()
10379 constraint (inst.operands[0].postind, in do_pld()
10381 constraint (inst.operands[0].writeback, in do_pld()
10383 constraint (!inst.operands[0].preind, in do_pld()
10392 constraint (!inst.operands[0].isreg, in do_pli()
10394 constraint (inst.operands[0].postind, in do_pli()
10396 constraint (inst.operands[0].writeback, in do_pli()
10398 constraint (!inst.operands[0].preind, in do_pli()
10407 constraint (inst.operands[0].writeback, in do_push_pop()
10506 constraint (inst.operands[2].shifted, in do_shift()
10517 constraint (value > 0xf, _("immediate too large (bigger than 0xF)")); in do_smc()
10540 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), in do_setpan()
10549 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan), in do_t_setpan()
10609 constraint (reg != REG_SP, _("SRS base register must be r13")); in do_srs()
10625 constraint (!inst.operands[2].isreg || !inst.operands[2].preind in do_strex()
10633 constraint (inst.operands[0].reg == inst.operands[1].reg in do_strex()
10636 constraint (inst.relocs[0].exp.X_op != O_constant in do_strex()
10649 constraint (!inst.operands[2].isreg || !inst.operands[2].preind in do_t_strexbh()
10655 constraint (inst.operands[0].reg == inst.operands[1].reg in do_t_strexbh()
10664 constraint (inst.operands[1].reg % 2 != 0, in do_strexd()
10666 constraint (inst.operands[2].present in do_strexd()
10671 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); in do_strexd()
10673 constraint (inst.operands[0].reg == inst.operands[1].reg in do_strexd()
10687 constraint (inst.operands[0].reg == inst.operands[1].reg in do_stlex()
10696 constraint (inst.operands[0].reg == inst.operands[1].reg in do_t_stlex()
10739 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) in do_vfp_sp_monadic()
10778 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) in do_vfp_reg_from_sp()
10789 constraint (inst.operands[2].imm != 2, in do_vfp_reg2_from_sp2()
10799 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) in do_vfp_sp_from_reg()
10810 constraint (inst.operands[0].imm != 2, in do_vfp_sp2_from_reg2()
10838 constraint (ldstm_type != VFP_LDSTMIA, in vfp_sp_ldstm()
10853 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, in vfp_dp_ldstm()
10905 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) in do_vfp_dp_rd_rm()
10930 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) in do_vfp_dp_rd_rn_rm()
10948 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) in do_vfp_dp_rm_rd_rn()
11054 constraint (inst.relocs[0].exp.X_op != O_constant in do_fpa_ldmstm()
11079 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); in do_iwmmxt_tandorc()
11158 constraint (inst.cond != COND_ALWAYS, BAD_COND); in do_iwmmxt_wldstw()
11213 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), in do_iwmmxt_wrwrwr_or_imm5()
11341 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); in do_xsc_mra()
11357 constraint (inst.operands[i].immisreg, in encode_thumb32_shifted_operand()
11364 constraint (inst.relocs[0].exp.X_op != O_constant, in encode_thumb32_shifted_operand()
11367 constraint (value > 32 in encode_thumb32_shifted_operand()
11396 constraint (!inst.operands[i].isreg, in encode_thumb32_addr_mode()
11402 constraint (is_pc, BAD_PC_ADDRESSING); in encode_thumb32_addr_mode()
11403 constraint (is_t || is_d, _("cannot use register index with this instruction")); in encode_thumb32_addr_mode()
11404 constraint (inst.operands[i].negative, in encode_thumb32_addr_mode()
11406 constraint (inst.operands[i].postind, in encode_thumb32_addr_mode()
11408 constraint (inst.operands[i].writeback, in encode_thumb32_addr_mode()
11410 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, in encode_thumb32_addr_mode()
11416 constraint (inst.relocs[0].exp.X_op != O_constant, in encode_thumb32_addr_mode()
11418 constraint (inst.relocs[0].exp.X_add_number < 0 in encode_thumb32_addr_mode()
11427 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); in encode_thumb32_addr_mode()
11428 constraint (is_t && inst.operands[i].writeback, in encode_thumb32_addr_mode()
11430 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0), in encode_thumb32_addr_mode()
11450 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); in encode_thumb32_addr_mode()
11451 constraint (is_t, _("cannot use post-indexing with this instruction")); in encode_thumb32_addr_mode()
11611 constraint (Rd == REG_PC, BAD_PC); in do_t_add_sub_w()
11652 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); in do_t_add_sub()
11689 constraint (inst.size_req == 2, _("cannot honor width suffix")); in do_t_add_sub()
11694 constraint ((inst.relocs[0].type in do_t_add_sub()
11701 constraint (add, BAD_PC); in do_t_add_sub()
11702 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, in do_t_add_sub()
11704 constraint (inst.relocs[0].exp.X_op != O_constant, in do_t_add_sub()
11706 constraint (inst.relocs[0].exp.X_add_number < 0 in do_t_add_sub()
11778 constraint (Rd == REG_PC, BAD_PC); in do_t_add_sub()
11780 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); in do_t_add_sub()
11781 constraint (Rs == REG_PC, BAD_PC); in do_t_add_sub()
11785 constraint (inst.operands[2].shifted && inst.operands[2].immisreg, in do_t_add_sub()
11790 constraint (Rd == REG_SP && Rs == REG_SP && value > 3, in do_t_add_sub()
11792 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, in do_t_add_sub()
11799 constraint (inst.instruction == T_MNEM_adds in do_t_add_sub()
11805 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) in do_t_add_sub()
11817 constraint (inst.operands[2].shifted, _("unshifted register required")); in do_t_add_sub()
11823 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); in do_t_add_sub()
11832 constraint (1, _("dest must overlap one source register")); in do_t_add_sub()
11944 constraint (inst.operands[2].shifted in do_t_arit3()
11958 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); in do_t_arit3()
11960 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, in do_t_arit3()
11962 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); in do_t_arit3()
11963 constraint (Rd != Rs, in do_t_arit3()
12041 constraint (inst.operands[2].shifted in do_t_arit3c()
12055 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); in do_t_arit3c()
12057 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, in do_t_arit3c()
12059 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); in do_t_arit3c()
12069 constraint (1, _("dest must overlap one source register")); in do_t_arit3c()
12078 constraint (msb > 32, _("bit-field extends past end of register")); in do_t_bfc()
12109 constraint (msb > 32, _("bit-field extends past end of register")); in do_t_bfi()
12130 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, in do_t_bfx()
12156 constraint (inst.operands[0].reg == REG_PC, BAD_PC); in do_t_blx()
12203 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2), in do_t_branch()
12236 constraint (inst.cond != COND_ALWAYS, in do_t_bkpt_hlt1()
12240 constraint (inst.operands[0].imm > range, in do_t_bkpt_hlt1()
12333 constraint (inst.cond != COND_ALWAYS, BAD_COND); in do_t_cond()
12345 constraint (Rn == REG_SP, BAD_SP); in do_t_cond()
12346 constraint (Rm == REG_SP, BAD_SP); in do_t_cond()
12356 constraint (Rn == REG_SP, BAD_SP); in do_t_cond()
12410 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) in do_t_cpsi()
12414 constraint (inst.operands[1].present || inst.size_req == 4, in do_t_cpsi()
12444 constraint (inst.operands[0].reg > 7, BAD_HIREG); in do_t_cbz()
12600 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED, in do_t_ldmstm()
12602 constraint (inst.operands[1].writeback, in do_t_ldmstm()
12695 constraint (inst.operands[0].reg > 7 in do_t_ldmstm()
12697 constraint (inst.instruction != T_MNEM_ldmia in do_t_ldmstm()
12728 constraint (!inst.operands[1].isreg || !inst.operands[1].preind in do_t_ldrex()
12734 constraint ((inst.operands[1].reg == REG_PC), BAD_PC); in do_t_ldrex()
12746 constraint (inst.operands[0].reg == REG_LR, in do_t_ldrexd()
12751 constraint (inst.operands[0].reg == inst.operands[1].reg, in do_t_ldrexd()
12856 constraint (inst.operands[1].writeback == 1 in do_t_ldst()
12867 constraint (inst.operands[0].reg > 7, BAD_HIREG); in do_t_ldst()
12872 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); in do_t_ldst()
12873 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg in do_t_ldst()
12886 constraint (!inst.operands[1].preind in do_t_ldst()
12892 constraint (inst.instruction & 0x0600, in do_t_ldst()
12894 constraint (inst.operands[1].reg == REG_PC in do_t_ldst()
12897 constraint (inst.operands[1].immisreg, in do_t_ldst()
12912 constraint (inst.operands[1].reg > 7, BAD_HIREG); in do_t_ldst()
12923 constraint (inst.operands[1].imm > 7, BAD_HIREG); in do_t_ldst()
12924 constraint (inst.operands[1].negative, in do_t_ldst()
12952 constraint (inst.operands[0].reg == REG_LR, in do_t_ldstd()
12954 constraint (inst.operands[0].reg == REG_R12, in do_t_ldstd()
13059 constraint (Rn == REG_PC, BAD_PC); in do_t_mov_cmp()
13068 constraint (Rm == REG_PC, BAD_PC); in do_t_mov_cmp()
13097 constraint (Rn == REG_PC, BAD_PC); in do_t_mov_cmp()
13098 constraint (Rm == REG_PC, BAD_PC); in do_t_mov_cmp()
13100 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); in do_t_mov_cmp()
13127 constraint ((inst.relocs[0].type in do_t_mov_cmp()
13240 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), in do_t_mov_cmp()
13283 constraint (inst.operands[1].shifted, in do_t_mov_cmp()
13311 constraint (Rn > 7, in do_t_mov_cmp()
13328 constraint (top, _(":lower16: not allowed in this instruction")); in do_t_mov16()
13333 constraint (!top, _(":upper16: not allowed in this instruction")); in do_t_mov16()
13361 constraint (Rn == REG_PC, BAD_PC); in do_t_mvn_tst()
13406 constraint (inst.operands[1].shifted in do_t_mvn_tst()
13418 constraint (inst.instruction > 0xffff in do_t_mvn_tst()
13420 constraint (!inst.operands[1].isreg || inst.operands[1].shifted, in do_t_mvn_tst()
13422 constraint (Rn > 7 || Rm > 7, in do_t_mvn_tst()
13464 constraint ((flags != 0) && m_profile, _("selected processor does " in do_t_mrs()
13470 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), in do_t_mrs()
13488 constraint (!inst.operands[1].isreg, in do_t_msr()
13505 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) in do_t_msr()
13513 constraint ((flags & 0xff) != 0, _("selected processor does not support " in do_t_msr()
13554 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); in do_t_mul()
13555 constraint (Rn > 7 || Rm > 7, in do_t_mul()
13571 constraint (1, _("dest must overlap one source register")); in do_t_mul()
13575 constraint (inst.instruction != T_MNEM_mul, in do_t_mul()
13640 constraint (inst.operands[0].present, in do_t_nop()
13677 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, in do_t_neg()
13679 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); in do_t_neg()
13714 constraint (inst.operands[2].shifted in do_t_orn()
13740 constraint (inst.relocs[0].exp.X_op != O_constant, in do_t_pkhbt()
13778 constraint (inst.operands[0].writeback, in do_t_push_pop()
13780 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED, in do_t_push_pop()
14016 constraint (inst.operands[2].shifted, in do_t_shift()
14048 constraint (inst.operands[2].shifted, in do_t_shift()
14068 constraint (inst.operands[0].reg > 7 in do_t_shift()
14070 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); in do_t_shift()
14074 constraint (inst.operands[2].reg > 7, BAD_HIREG); in do_t_shift()
14075 constraint (inst.operands[0].reg != inst.operands[1].reg, in do_t_shift()
14091 constraint (inst.operands[2].shifted, in do_t_shift()
14151 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), in do_t_smc()
14153 constraint (inst.relocs[0].exp.X_op != O_constant, in do_t_smc()
14155 constraint (value > 0xf, _("immediate too large (bigger than 0xF)")); in do_t_smc()
14195 constraint (inst.relocs[0].exp.X_op != O_constant, in do_t_ssat_usat()
14200 constraint (shift_amount > 31, in do_t_ssat_usat()
14237 constraint (!inst.operands[2].isreg || !inst.operands[2].preind in do_t_strex()
14243 constraint (inst.operands[2].reg == REG_PC, BAD_PC); in do_t_strex()
14257 constraint (inst.operands[0].reg == inst.operands[1].reg in do_t_strexd()
14317 constraint (inst.operands[2].present && inst.operands[2].imm != 0, in do_t_sxth()
14319 constraint (1, BAD_HIREG); in do_t_sxth()
14337 constraint (inst.operands[0].immisreg, in do_t_tb()
14344 constraint (Rn == REG_SP, BAD_SP); in do_t_tb()
14347 constraint (!half && inst.operands[0].shifted, in do_t_tb()
14360 constraint (inst.size_req == 2, in do_t_udf()
14497 constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS); in do_t_branch_future()
14508 constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS); in do_t_branch_future()
14514 constraint (inst.cond != COND_ALWAYS, BAD_COND); in do_t_branch_future()
14566 constraint (inst.operands[3].reg == inst.operands[0].reg, BAD_OVERLAP); in do_mve_scalar_shift1()
14567 constraint (inst.operands[3].reg == inst.operands[1].reg, BAD_OVERLAP); in do_mve_scalar_shift1()
14587 constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP); in do_mve_scalar_shift()
14588 constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP); in do_mve_scalar_shift()
15670 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, in do_vfp_nsyn_opcode()
16066 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); in do_mve_vpt()
16073 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), in do_mve_vpt()
16075 constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE); in do_mve_vpt()
16081 constraint (et.size != 8 && et.size != 16 && et.size != 32, in do_mve_vpt()
16118 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); in do_mve_vcmp()
16123 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); in do_mve_vcmp()
16143 constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC in do_mve_vcmp()
16154 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), in do_mve_vcmp()
16238 constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8, in do_mve_viddup()
16252 constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN); in do_mve_viddup()
16311 constraint (imm < 1 || (unsigned)imm > et.size, in do_mve_vshll()
16347 constraint (imm < 1 || imm > 32, _("immediate value out of range")); in do_mve_vshlc()
16394 constraint (imm < 1 || ((unsigned) imm) > (et.size / 2), in do_mve_vshrn()
16494 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, in do_mve_vcmul()
16538 constraint (!inst.operands[0].present, in do_t_loloop()
16555 constraint (inst.operands[1].isreg != 1, BAD_ARGS); in do_t_loloop()
16558 constraint (inst.operands[1].reg == REG_PC, BAD_PC); in do_t_loloop()
16584 constraint (inst.operands[2].present, BAD_SYNTAX); in do_vfp_nsyn_cmp()
16585 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd), in do_vfp_nsyn_cmp()
16791 constraint (inst.operands[3].reg > 14, MVE_BAD_QREG); in mve_encode_rrqq()
17037 constraint (imm < 0 || (unsigned)imm >= et.size, in do_neon_shl()
17060 constraint (inst.operands[0].reg != inst.operands[1].reg, in do_neon_shl()
17117 constraint (imm < 0 || (unsigned)imm >= et.size, in do_neon_qshl()
17140 constraint (inst.operands[0].reg != inst.operands[1].reg, in do_neon_qshl()
17197 constraint (inst.operands[0].reg != inst.operands[1].reg, in do_neon_rshl()
17331 constraint (inst.operands[0].reg != inst.operands[1].reg, in do_neon_logic()
17441 constraint (size < 32, BAD_ADDR_MODE); in do_mve_vstr_vldr_QI()
17442 constraint (size != elsize, BAD_EL_TYPE); in do_mve_vstr_vldr_QI()
17443 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); in do_mve_vstr_vldr_QI()
17444 constraint (!inst.operands[1].preind, BAD_ADDR_MODE); in do_mve_vstr_vldr_QI()
17445 constraint (load && inst.operands[0].reg == inst.operands[1].reg, in do_mve_vstr_vldr_QI()
17456 constraint ((imm % (size / 8) != 0) in do_mve_vstr_vldr_QI()
17480 constraint (os != 0 && size == 8, in do_mve_vstr_vldr_RQ()
17482 constraint (os && os != neon_logbits (size), in do_mve_vstr_vldr_RQ()
17491 constraint (elsize >= 64, BAD_EL_TYPE); in do_mve_vstr_vldr_RQ()
17494 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE); in do_mve_vstr_vldr_RQ()
17498 constraint (elsize != size, BAD_EL_TYPE); in do_mve_vstr_vldr_RQ()
17503 constraint (inst.operands[1].writeback || !inst.operands[1].preind, in do_mve_vstr_vldr_RQ()
17507 constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f), in do_mve_vstr_vldr_RQ()
17510 constraint (size == elsize && type == NT_signed, BAD_EL_TYPE); in do_mve_vstr_vldr_RQ()
17511 constraint (size != elsize && type != NT_unsigned && type != NT_signed, in do_mve_vstr_vldr_RQ()
17517 constraint (type != NT_untyped, BAD_EL_TYPE); in do_mve_vstr_vldr_RQ()
17535 constraint (size >= 64, BAD_ADDR_MODE); in do_mve_vstr_vldr_RI()
17539 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE); in do_mve_vstr_vldr_RI()
17542 constraint (elsize != size, BAD_EL_TYPE); in do_mve_vstr_vldr_RI()
17549 constraint (elsize != size && type != NT_unsigned in do_mve_vstr_vldr_RI()
17554 constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE); in do_mve_vstr_vldr_RI()
17570 constraint (1, _("immediate must be in the range of +/-[0,127]")); in do_mve_vstr_vldr_RI()
17573 constraint (1, _("immediate must be a multiple of 2 in the" in do_mve_vstr_vldr_RI()
17577 constraint (1, _("immediate must be a multiple of 4 in the" in do_mve_vstr_vldr_RI()
17585 constraint (inst.operands[1].reg > 7, BAD_HIREG); in do_mve_vstr_vldr_RI()
17586 constraint (inst.operands[0].reg > 14, in do_mve_vstr_vldr_RI()
17673 constraint (1, BAD_ADDR_MODE); in do_mve_vstr_vldr()
17685 constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0 in do_mve_vst_vld()
17689 constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE); in do_mve_vst_vld()
17732 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); in do_mve_vaddlv()
17748 constraint ((inst.instruction == ((unsigned) N_MNEM_vmax) in do_neon_dyadic_if_su()
17771 constraint (rs == NS_QQR && et.size == 64, BAD_FPU); in do_neon_addsub_if_i()
17945 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); in do_neon_mac_maybe_scalar()
17954 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); in do_neon_mac_maybe_scalar()
17963 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); in do_neon_mac_maybe_scalar()
17973 constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU)); in do_bfloat_vfma()
17974 constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16)); in do_bfloat_vfma()
17991 constraint (!(idx < 4), _("index must be in the range 0 to 3")); in do_bfloat_vfma()
17993 constraint (!(inst.operands[2].reg < 8), in do_bfloat_vfma()
18045 constraint (!inst.operands[2].isvec, BAD_FPU); in do_neon_fmac()
18057 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); in do_mve_vfma()
18093 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); in do_neon_mul()
18104 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext), in do_neon_mul()
18111 constraint (!inst.operands[2].isvec, BAD_FPU); in do_neon_mul()
18126 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); in do_neon_qdmulh()
18174 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG); in do_mve_vaddv()
18192 constraint (rot != 90 && rot != 270, _("immediate out of range")); in do_mve_vhcadd()
18343 constraint (rs != NS_QQQ, BAD_FPU); in do_mve_vmull()
18412 constraint (inst.operands[2].reg > 14, in do_mve_vmladav()
18480 constraint (inst.operands[1].reg == REG_SP, BAD_SP); in do_mve_vrmlaldavh()
18487 constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN); in do_mve_vrmlaldavh()
18488 constraint (inst.operands[1].reg == REG_PC, BAD_PC); in do_mve_vrmlaldavh()
18663 constraint (imm < 0 || (unsigned)imm >= et.size, in do_neon_sli()
18688 constraint (imm < 1 || (unsigned)imm > et.size, in do_neon_sri()
18714 constraint (imm < 0 || (unsigned)imm >= et.size, in do_neon_qshlu_imm()
18771 constraint (imm < 1 || (unsigned)imm > et.size, in do_neon_rshift_sat_narrow()
18798 constraint (imm < 1 || (unsigned)imm > et.size, in do_neon_rshift_sat_narrow_u()
18835 constraint (imm < 1 || (unsigned)imm > et.size, in do_neon_rshift_narrow()
18982 constraint (inst.operands[0].reg != inst.operands[1].reg, in do_vfp_nsyn_cvt()
19042 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), in do_vfp_nsyn_cvt_fpv8()
19047 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16), in do_vfp_nsyn_cvt_fpv8()
19197 constraint (inst.operands[2].present && inst.operands[2].imm == 0, in do_neon_cvt_1()
19205 constraint (inst.operands[2].imm > 16, in do_neon_cvt_1()
19212 constraint (inst.operands[2].imm > 32, in do_neon_cvt_1()
19367 constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16)); in do_neon_cvt_1()
19510 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), in do_neon_cvttb_1()
19520 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), in do_neon_cvttb_1()
19528 constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16)); in do_neon_cvttb_1()
19560 constraint (et.type == NT_invtype, in neon_move_immediate()
19570 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, in neon_move_immediate()
19637 constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU); in do_neon_mvn()
19809 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml), in do_neon_fmac_maybe_scalar_long()
19812 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), in do_neon_fmac_maybe_scalar_long()
19931 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), in do_neon_ext()
19972 constraint (et.size >= elsize, in do_neon_rev()
19982 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1), in do_neon_dup()
20017 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1), in do_neon_dup()
20064 constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2, in do_mve_mov()
20067 constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg, in do_mve_mov()
20069 constraint (inst.operands[Rt].reg == REG_SP in do_mve_mov()
20072 constraint (inst.operands[Rt].reg == REG_PC in do_mve_mov()
20252 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) in do_neon_mov()
20266 constraint (et.type == NT_invtype, _("bad type for scalar")); in do_neon_mov()
20267 constraint (x >= size / et.size, _("scalar index out of range")); in do_neon_mov()
20292 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) in do_neon_mov()
20334 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1) in do_neon_mov()
20349 constraint (et.type == NT_invtype, _("bad type for scalar")); in do_neon_mov()
20350 constraint (x >= size / et.size, _("scalar index out of range")); in do_neon_mov()
20373 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) in do_neon_mov()
20453 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) in do_neon_mov()
20456 constraint (inst.operands[3].reg != inst.operands[2].reg + 1, in do_neon_mov()
20464 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2) in do_neon_mov()
20467 constraint (inst.operands[1].reg != inst.operands[0].reg + 1, in do_neon_mov()
20548 constraint (imm < 1 || (unsigned)imm > et.size, in do_neon_rshift_round_imm()
20558 constraint (rs != NS_HH, _("invalid suffix")); in do_neon_movhf()
20731 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd) in do_neon_ldm_stm()
20744 constraint (is_dbmode && !inst.operands[0].writeback, in do_neon_ldm_stm()
20747 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, in do_neon_ldm_stm()
20764 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd), _(BAD_FPU)); in do_vfp_nsyn_push_pop_check()
20768 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 32, in do_vfp_nsyn_push_pop_check()
20773 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, in do_vfp_nsyn_push_pop_check()
20958 constraint (typebits == -1, _("bad list type for instruction")); in do_neon_ld_st_interleave()
20959 constraint (((inst.instruction >> 8) & 3) && et.size == 64, in do_neon_ld_st_interleave()
21020 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, in do_neon_ld_st_lane()
21022 constraint (NEON_LANE (inst.operands[0].imm) >= max_el, in do_neon_ld_st_lane()
21024 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 in do_neon_ld_st_lane()
21058 constraint (inst.operands[1].immisalign, in do_neon_ld_st_lane()
21126 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, in do_neon_ld_dup()
21134 constraint (inst.operands[1].immisalign, in do_neon_ld_dup()
21136 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, in do_neon_ld_dup()
21150 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, in do_neon_ld_dup()
21174 constraint (inst.operands[1].reg == REG_PC, BAD_PC); in do_neon_ldx_stx()
21206 constraint (!inst.operands[1].immisreg, in do_neon_ldx_stx()
21208 constraint (postreg == 0xd || postreg == 0xf, in do_neon_ldx_stx()
21214 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE); in do_neon_ldx_stx()
21215 constraint (inst.relocs[0].exp.X_op != O_constant in do_neon_ldx_stx()
21240 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), in do_vfp_nsyn_fpv8()
21298 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), in do_vrint_1()
21438 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) in do_vcmla()
21441 constraint (inst.relocs[0].exp.X_op != O_constant, in do_vcmla()
21444 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270, in do_vcmla()
21498 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) in do_vcadd()
21501 constraint (inst.relocs[0].exp.X_op != O_constant, in do_vcadd()
21505 constraint (rot != 90 && rot != 270, _("immediate out of range")); in do_vcadd()
21540 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU); in do_vcadd()
21567 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8), in do_neon_dotproduct()
21639 constraint ((idx != 1 && idx != 0), _("index must be 0 or 1")); in do_vusdot()
21641 constraint (!(inst.operands[2].reg < 16), in do_vusdot()
21667 constraint ((idx != 1 && idx != 0), _("index must be 0 or 1")); in do_vsudot()
21669 constraint (!(inst.operands[2].reg < 16), in do_vsudot()
21706 constraint ( in check_cde_operand()
21710 constraint ( !((Rx <= 10 && Rx % 2 == 0 )), in check_cde_operand()
21736 constraint (coproc > 7, _("CDE Coprocessor must be in range 0-7")); in cde_handle_coproc()
21737 constraint (!(cde_coproc_enabled (coproc)), BAD_CDE_COPROC); in cde_handle_coproc()
21760 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE)); in do_custom_instruction_1()
21769 constraint (inst.operands[2].reg != Rd + 1, in do_custom_instruction_1()
21791 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE)); in do_custom_instruction_2()
21799 constraint (inst.operands[2].reg != Rd + 1, in do_custom_instruction_2()
21830 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE)); in do_custom_instruction_3()
21838 constraint (inst.operands[2].reg != Rd + 1, in do_custom_instruction_3()
22031 constraint (R >= 16, _("'q' register must be in range 0-7")); in vcx_ensure_register_in_range()
22034 constraint (R >= 16, _("'d' register must be in range 0-15")); in vcx_ensure_register_in_range()
22036 constraint (R >= 32, _("'s' register must be in range 0-31")); in vcx_ensure_register_in_range()
22084 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE)); in vcx_handle_common_checks()
22090 constraint (!mark_feature_used (&mve_ext), in vcx_handle_common_checks()
22093 constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp, cpu_variant) in vcx_handle_common_checks()
22111 constraint (imm >= 2048, in do_vcx1()
22127 constraint (imm >= 64, in do_vcx2()
22142 constraint (imm >= 8, in do_vcx3()
22329 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8), in do_vjcvt()
22340 constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU)); in do_vdot()
22349 constraint ((idx != 1 && idx != 0), _("index must be 0 or 1")); in do_vdot()
22351 constraint (!(inst.operands[2].reg < 16), in do_vdot()
22370 constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU)); in do_vmmla()
22385 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, pacbti_ext), in do_t_pacbti_nonop()
22397 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, pacbti_ext), in do_t_pacbti_pacg()