38 static unsigned insertUndefLaneMask(MachineBasicBlock &MBB);
86   void buildMergeLaneMasks(MachineBasicBlock &MBB,
90   getSaluInsertionAtEnd(MachineBasicBlock &MBB) const;
140   bool isSource(MachineBasicBlock &MBB) const {  in isSource()
141     return ReachableMap.find(&MBB)->second;  in isSource()
158     for (MachineBasicBlock *MBB : IncomingBlocks) {  in analyze()
159       if (MBB == &DefBlock) {  in analyze()
164       ReachableMap.try_emplace(MBB, false);  in analyze()
165       ReachableOrdered.push_back(MBB);  in analyze()
170       for (MachineInstr &MI : MBB->terminators()) {  in analyze()
180       if (Divergent && PDT.dominates(&DefBlock, MBB))  in analyze()
181         append_range(Stack, MBB->successors());  in analyze()
185       MachineBasicBlock *MBB = Stack.pop_back_val();  in analyze()  local
186       if (!ReachableMap.try_emplace(MBB, false).second)  in analyze()
188       ReachableOrdered.push_back(MBB);  in analyze()
190       append_range(Stack, MBB->successors());  in analyze()
193     for (MachineBasicBlock *MBB : ReachableOrdered) {  in analyze()
195       for (MachineBasicBlock *Pred : MBB->predecessors()) {  in analyze()
203         ReachableMap[MBB] = true;  in analyze()
276   void initialize(MachineBasicBlock &MBB) {  in initialize()  argument
284     DefBlock = &MBB;  in initialize()
318     for (MachineBasicBlock *MBB : Blocks)
319       Dom = DT.findNearestCommonDominator(Dom, MBB);
334   bool inLoopLevel(MachineBasicBlock &MBB, unsigned LoopLevel,  in inLoopLevel()  argument
336     auto DomIt = Visited.find(&MBB);  in inLoopLevel()
340     if (llvm::is_contained(Blocks, &MBB))  in inLoopLevel()
371       MachineBasicBlock *MBB = Stack.pop_back_val();  in advanceLevel()  local
372       if (!PDT.dominates(VisitedPostDom, MBB))  in advanceLevel()
373         NextLevel.push_back(MBB);  in advanceLevel()
375       Visited[MBB] = Level;  in advanceLevel()
376       VisitedDom = DT.findNearestCommonDominator(VisitedDom, MBB);  in advanceLevel()
378       for (MachineBasicBlock *Succ : MBB->successors()) {  in advanceLevel()
380           if (MBB == VisitedPostDom)  in advanceLevel()
388           if (MBB == VisitedPostDom)  in advanceLevel()
424 static unsigned insertUndefLaneMask(MachineBasicBlock &MBB) {  in insertUndefLaneMask()  argument
425   MachineFunction &MF = *MBB.getParent();  in insertUndefLaneMask()
429   BuildMI(MBB, MBB.getFirstTerminator(), {}, TII->get(AMDGPU::IMPLICIT_DEF),  in insertUndefLaneMask()
499   for (MachineBasicBlock &MBB : *MF) {  in lowerCopiesFromI1()
500     for (MachineInstr &MI : MBB) {  in lowerCopiesFromI1()
520       BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)  in lowerCopiesFromI1()
547   for (MachineBasicBlock &MBB : *MF) {  in lowerPhis()
548     for (MachineInstr &MI : MBB.phis()) {  in lowerPhis()
556     MachineBasicBlock &MBB = *MI->getParent();  in lowerPhis()  local
557     if (&MBB != PrevMBB) {  in lowerPhis()
558       LF.initialize(MBB);  in lowerPhis()
559       PrevMBB = &MBB;  in lowerPhis()
595     std::vector<MachineBasicBlock *> DomBlocks = {&MBB};  in lowerPhis()
623       PIA.analyze(MBB, IncomingBlocks);  in lowerPhis()
625       for (MachineBasicBlock *MBB : PIA.predecessors())  in lowerPhis()
626         SSAUpdater.AddAvailableValue(MBB, insertUndefLaneMask(*MBB));  in lowerPhis()
650     Register NewReg = SSAUpdater.GetValueInMiddleOfBlock(&MBB);  in lowerPhis()
667   for (MachineBasicBlock &MBB : *MF) {  in lowerCopiesToI1()
668     LF.initialize(MBB);  in lowerCopiesToI1()
670     for (MachineInstr &MI : MBB) {  in lowerCopiesToI1()
698         BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg)  in lowerCopiesToI1()
707       std::vector<MachineBasicBlock *> DomBlocks = {&MBB};  in lowerCopiesToI1()
716         SSAUpdater.AddAvailableValue(&MBB, DstReg);  in lowerCopiesToI1()
719         buildMergeLaneMasks(MBB, MI, DL, DstReg,  in lowerCopiesToI1()
720                             SSAUpdater.GetValueInMiddleOfBlock(&MBB), SrcReg);  in lowerCopiesToI1()
781 SILowerI1Copies::getSaluInsertionAtEnd(MachineBasicBlock &MBB) const {  in getSaluInsertionAtEnd()
782   auto InsertionPt = MBB.getFirstTerminator();  in getSaluInsertionAtEnd()
784   for (auto I = InsertionPt, E = MBB.end(); I != E; ++I) {  in getSaluInsertionAtEnd()
794   while (InsertionPt != MBB.begin()) {  in getSaluInsertionAtEnd()
807 void SILowerI1Copies::buildMergeLaneMasks(MachineBasicBlock &MBB,  in buildMergeLaneMasks()  argument
818       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);  in buildMergeLaneMasks()
820       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);  in buildMergeLaneMasks()
822       BuildMI(MBB, I, DL, TII->get(XorOp), DstReg)  in buildMergeLaneMasks()
836       BuildMI(MBB, I, DL, TII->get(AndN2Op), PrevMaskedReg)  in buildMergeLaneMasks()
847       BuildMI(MBB, I, DL, TII->get(AndOp), CurMaskedReg)  in buildMergeLaneMasks()
854     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
857     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
860     BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg)  in buildMergeLaneMasks()
864     BuildMI(MBB, I, DL, TII->get(OrOp), DstReg)  in buildMergeLaneMasks()