Lines Matching refs:AMDGPU
3 let Namespace = "AMDGPU";
16 let Namespace = "AMDGPU";
22 let Namespace = "AMDGPU";
31 let Namespace = "AMDGPU";
152 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
165 def R600_Addr : RegisterClass <"AMDGPU", [i32], 32, (add (sequence "Addr%u_X", 0, 127))>;
170 def R600_Addr_Y : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Y)>;
171 def R600_Addr_Z : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Z)>;
172 def R600_Addr_W : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_W)>;
174 def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
177 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
180 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
183 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
186 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
189 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
193 def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
196 def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
199 def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
202 def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,
205 def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32,
211 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
214 def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
217 def R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
220 def R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32,
223 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
227 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
236 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
239 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
242 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
247 def R600_Reg128Vertical : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
251 def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32, i64, f64], 64,
254 def R600_Reg64Vertical : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,