42                                            unsigned &SubIdx) const {  in isCoalescableExtInstr()
48                                              int &FrameIndex) const {  in isLoadFromStackSlot()
54                                                    int &FrameIndex) const {  in isLoadFromStackSlotPostFE()
61                                           int &FrameIndex) const {  in hasLoadFromStackSlot()
66                                               int &FrameIndex) const {  in isStoreFromStackSlot()
71                                                     int &FrameIndex) const {  in isStoreFromStackSlotPostFE()
77                                            int &FrameIndex) const {  in hasStoreFromStackSlot()
85                                       LiveVariables *LV) const {  in convertToThreeAddress()
96                                     const TargetRegisterInfo *TRI) const {  in storeRegToStackSlot()  argument
105                                      const TargetRegisterInfo *TRI) const {  in loadRegFromStackSlot()  argument
109 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {  in expandPostRAPseudo()
160                                       int FrameIndex) const {  in foldMemoryOperandImpl()
168                                       MachineInstr *LoadMI) const {  in foldMemoryOperandImpl()
174                                      const SmallVectorImpl<unsigned> &Ops) const {  in canFoldMemoryOperand()  argument
182                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {  in unfoldMemoryOperand()
189                                     SmallVectorImpl<SDNode*> &NewNodes) const {  in unfoldMemoryOperand()
197                                            unsigned *LoadRegIndex) const {  in getOpcodeAfterMemoryUnfold()
218                                               unsigned NumLoads) const {  in shouldScheduleLoadsNear()
229 AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)  in ReverseBranchCondition()
235                                 MachineBasicBlock::iterator MI) const {  in insertNoop()
239 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {  in isPredicated()  argument
245                                   const SmallVectorImpl<MachineOperand> &Pred2)  in SubsumesPredicate()
252                                       std::vector<MachineOperand> &Pred) const {  in DefinesPredicate()
257 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {  in isPredicable()
263 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {  in isSafeToMoveRegClassDefs()  argument
268 bool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const {  in isRegisterStore()  argument
272 bool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const {  in isRegisterLoad()  argument
276 int AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {  in getIndirectIndexBegin()  argument
311 int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {  in getIndirectIndexEnd()  argument
330 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {  in getMaskedMIMGOp()
365 int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const {  in pseudoToMCOpcode()