Lines Matching full:op
31 // FWDBWD: %[[v1:.*]] = "slicing-test-op"() : () -> i1
32 // FWDBWD: %[[v2:.*]] = "slicing-test-op"() : () -> i2
33 // FWDBWD: %[[v3:.*]] = "slicing-test-op"() : () -> i3
34 // FWDBWD: %[[v4:.*]] = "slicing-test-op"() : () -> i4
35 // FWDBWD: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
36 // FWDBWD: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
37 // FWDBWD: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
38 // FWDBWD: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
39 // FWDBWD: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
41 %1 = "slicing-test-op" () : () -> i1
52 // FWDBWD: %[[v1:.*]] = "slicing-test-op"() : () -> i1
53 // FWDBWD: %[[v2:.*]] = "slicing-test-op"() : () -> i2
54 // FWDBWD: %[[v3:.*]] = "slicing-test-op"() : () -> i3
55 // FWDBWD: %[[v4:.*]] = "slicing-test-op"() : () -> i4
56 // FWDBWD: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
57 // FWDBWD: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
58 // FWDBWD: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
59 // FWDBWD: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
60 // FWDBWD: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
62 %2 = "slicing-test-op" () : () -> i2
72 // FWDBWD: %[[v1:.*]] = "slicing-test-op"() : () -> i1
73 // FWDBWD: %[[v2:.*]] = "slicing-test-op"() : () -> i2
74 // FWDBWD: %[[v3:.*]] = "slicing-test-op"() : () -> i3
75 // FWDBWD: %[[v4:.*]] = "slicing-test-op"() : () -> i4
76 // FWDBWD: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
77 // FWDBWD: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
78 // FWDBWD: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
79 // FWDBWD: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
80 // FWDBWD: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
82 %3 = "slicing-test-op" () : () -> i3
92 // FWDBWD: %[[v1:.*]] = "slicing-test-op"() : () -> i1
93 // FWDBWD: %[[v2:.*]] = "slicing-test-op"() : () -> i2
94 // FWDBWD: %[[v3:.*]] = "slicing-test-op"() : () -> i3
95 // FWDBWD: %[[v4:.*]] = "slicing-test-op"() : () -> i4
96 // FWDBWD: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
97 // FWDBWD: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
98 // FWDBWD: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
99 // FWDBWD: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
100 // FWDBWD: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
102 %4 = "slicing-test-op" () : () -> i4
110 // BWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
111 // BWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
114 // FWDBWD: %[[v1:.*]] = "slicing-test-op"() : () -> i1
115 // FWDBWD: %[[v2:.*]] = "slicing-test-op"() : () -> i2
116 // FWDBWD: %[[v3:.*]] = "slicing-test-op"() : () -> i3
117 // FWDBWD: %[[v4:.*]] = "slicing-test-op"() : () -> i4
118 // FWDBWD: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
119 // FWDBWD: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
120 // FWDBWD: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
121 // FWDBWD: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
122 // FWDBWD: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
124 %5 = "slicing-test-op" (%1, %2) : (i1, i2) -> i5
131 // BWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
132 // BWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
135 // FWDBWD: %[[v1:.*]] = "slicing-test-op"() : () -> i1
136 // FWDBWD: %[[v2:.*]] = "slicing-test-op"() : () -> i2
137 // FWDBWD: %[[v3:.*]] = "slicing-test-op"() : () -> i3
138 // FWDBWD: %[[v4:.*]] = "slicing-test-op"() : () -> i4
139 // FWDBWD: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
140 // FWDBWD: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
141 // FWDBWD: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
142 // FWDBWD: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
143 // FWDBWD: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
145 %6 = "slicing-test-op" (%3, %4) : (i3, i4) -> i6
151 // BWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
152 // BWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
153 // BWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
156 // FWDBWD: %[[v1:.*]] = "slicing-test-op"() : () -> i1
157 // FWDBWD: %[[v2:.*]] = "slicing-test-op"() : () -> i2
158 // FWDBWD: %[[v3:.*]] = "slicing-test-op"() : () -> i3
159 // FWDBWD: %[[v4:.*]] = "slicing-test-op"() : () -> i4
160 // FWDBWD: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
161 // FWDBWD: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
162 // FWDBWD: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
163 // FWDBWD: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
164 // FWDBWD: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
166 %7 = "slicing-test-op" (%1, %5) : (i1, i5) -> i7
172 // BWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
173 // BWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
174 // BWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
175 // BWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
176 // BWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
177 // BWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
180 // FWDBWD: %[[v1:.*]] = "slicing-test-op"() : () -> i1
181 // FWDBWD: %[[v2:.*]] = "slicing-test-op"() : () -> i2
182 // FWDBWD: %[[v3:.*]] = "slicing-test-op"() : () -> i3
183 // FWDBWD: %[[v4:.*]] = "slicing-test-op"() : () -> i4
184 // FWDBWD: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
185 // FWDBWD: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
186 // FWDBWD: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
187 // FWDBWD: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
188 // FWDBWD: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
190 %8 = "slicing-test-op" (%5, %6) : (i5, i6) -> i8
195 // BWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
196 // BWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
197 // BWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
198 // BWD-NEXT: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
199 // BWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
200 // BWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
201 // BWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
202 // BWD-NEXT: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
205 // FWDBWD: %[[v1:.*]] = "slicing-test-op"() : () -> i1
206 // FWDBWD: %[[v2:.*]] = "slicing-test-op"() : () -> i2
207 // FWDBWD: %[[v3:.*]] = "slicing-test-op"() : () -> i3
208 // FWDBWD: %[[v4:.*]] = "slicing-test-op"() : () -> i4
209 // FWDBWD: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
210 // FWDBWD: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
211 // FWDBWD: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
212 // FWDBWD: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
213 // FWDBWD: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
215 %9 = "slicing-test-op" (%7, %8) : (i7, i8) -> i9
237 // affine.for appears as a proper op in the backward slice
239 %b = "slicing-test-op"(%i1): (index) -> index
249 %c = "slicing-test-op"(%i0): (index) -> index
262 %c = "slicing-test-op"(%f): (f32) -> index
267 %d = "slicing-test-op"(%c, %i2): (index, index) -> index
279 %0 = "slicing-test-op"(%arg0, %arg0): (index, index) -> index
290 …// FWD: matched: %{{.*}}:2 = "slicing-test-op"(%arg0, %arg0) : (index, index) -> (index, index) fo…
292 %0:2 = "slicing-test-op"(%arg0, %arg0): (index, index) -> (index, index)