Lines Matching defs:ProcModel
110 unsigned emitRegisterFileTables(const CodeGenProcModel &ProcModel,
112 void emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
114 void emitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
118 void emitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
120 void emitProcessorResources(const CodeGenProcModel &ProcModel,
123 const CodeGenProcModel &ProcModel);
125 const CodeGenProcModel &ProcModel);
129 const CodeGenProcModel &ProcModel);
130 void genSchedClassTables(const CodeGenProcModel &ProcModel,
479 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
481 if (!ItinsDefSet.insert(ProcModel.ItinsDef).second)
484 ConstRecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU");
488 StringRef Name = ProcModel.ItinsDef->getName();
498 ConstRecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
533 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
539 if (!ProcModel.hasItineraries())
542 StringRef Name = ProcModel.ItinsDef->getName();
545 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");
551 const Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
713 const CodeGenProcModel &ProcModel, raw_ostream &OS) {
714 OS << "\nstatic const unsigned " << ProcModel.ModelName
718 for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) {
719 const Record *PRDef = ProcModel.ProcResourceDefs[I];
724 SchedModels.findProcResUnits(RUDef, ProcModel, PRDef->getLoc());
726 OS << " " << ProcModel.getProcResourceIdx(RU) << ", ";
734 static void emitRetireControlUnitInfo(const CodeGenProcModel &ProcModel,
737 if (const Record *RCU = ProcModel.RetireControlUnit) {
748 static void emitRegisterFileInfo(const CodeGenProcModel &ProcModel,
752 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles);
758 OS << ProcModel.ModelName << "RegisterCosts,\n ";
765 SubtargetEmitter::emitRegisterFileTables(const CodeGenProcModel &ProcModel,
767 if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) {
774 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName
778 for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) {
797 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName
803 for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) {
817 void SubtargetEmitter::emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
820 if (ProcModel.LoadQueue) {
821 const Record *Queue = ProcModel.LoadQueue->getValueAsDef("QueueDescriptor");
822 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),
823 find(ProcModel.ProcResourceDefs, Queue));
828 if (ProcModel.StoreQueue) {
830 ProcModel.StoreQueue->getValueAsDef("QueueDescriptor");
831 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),
832 find(ProcModel.ProcResourceDefs, Queue));
837 void SubtargetEmitter::emitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
841 unsigned NumCostEntries = emitRegisterFileTables(ProcModel, OS);
844 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName
848 emitRetireControlUnitInfo(ProcModel, OS);
852 emitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(),
856 emitLoadStoreQueueInfo(ProcModel, OS);
861 void SubtargetEmitter::emitProcessorResources(const CodeGenProcModel &ProcModel,
863 emitProcessorResourceSubUnits(ProcModel, OS);
866 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName
872 for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) {
873 const Record *PRDef = ProcModel.ProcResourceDefs[I];
889 ProcModel, PRDef->getLoc());
890 SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
900 OS << ProcModel.ModelName << "ProcResourceSubUnits + "
917 const CodeGenProcModel &ProcModel) {
930 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
937 ProcModel.ModelName +
947 auto I = ProcModel.WriteResMap.find(SchedWrite.TheDef);
948 if (I != ProcModel.WriteResMap.end())
952 I = ProcModel.WriteResMap.find(AliasDef);
953 if (I != ProcModel.WriteResMap.end()) {
958 ProcModel.ModelName);
963 // TODO: If ProcModel has a base model (previous generation processor),
966 PrintFatalError(ProcModel.ModelDef->getLoc(),
977 const CodeGenProcModel &ProcModel) {
989 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
996 ProcModel.ModelName +
1006 auto I = ProcModel.ReadAdvanceMap.find(SchedRead.TheDef);
1007 if (I != ProcModel.ReadAdvanceMap.end())
1011 I = ProcModel.ReadAdvanceMap.find(AliasDef);
1012 if (I != ProcModel.ReadAdvanceMap.end()) {
1018 ProcModel.ModelName);
1023 // TODO: If ProcModel has a base model (previous generation processor),
1026 PrintFatalError(ProcModel.ModelDef->getLoc(),
1083 void SubtargetEmitter::genSchedClassTables(const CodeGenProcModel &ProcModel,
1087 if (!ProcModel.hasInstrSchedModel())
1107 if (CGT.ProcIndex == ProcModel.Index) {
1122 if (!is_contained(SC.ProcIndices, ProcModel.Index))
1133 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {
1147 for (const Record *I : ProcModel.ItinRWDefs) {
1156 LLVM_DEBUG(dbgs() << ProcModel.ModelName
1169 SchedModels.expandRWSeqForProc(W, WriteSeq, /*IsRead=*/false, ProcModel);
1178 if (!ProcModel.hasReadOfWrite(SchedModels.getSchedWrite(WriteID).TheDef))
1184 findWriteResources(SchedModels.getSchedWrite(WS), ProcModel);
1246 expandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel);
1252 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
1300 findReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
1573 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
1574 genSchedClassTables(ProcModel, SchedTables);