Lines Matching defs:EnumValue

125     OS << "  " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
126   assert(Registers.size() == Registers.back().EnumValue &&
145       OS << "  " << RC.getIdName() << " = " << RC.EnumValue << ",\n";
613   OS << (Idx ? Idx->EnumValue : 0);
647     unsigned Cur = (*I)->EnumValue;
666     CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1];
673     auto *&Entry = Vec[I.first->EnumValue - 1];
674     assert((!Entry || Entry == I.second) && "Expected EnumValue to be unique");
899     diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());
910     diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(),
1020         BVE.add(RegBank.getReg(Reg)->EnumValue);
1273         assert(RC.EnumValue == EV && "Unexpected order of register classes");
1320       IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];
1395          << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n    ";
1448       InAllocClass.set(Reg.EnumValue);
1503           OS << "      " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
1538         unsigned EnumValue = 0;
1541           EnumValue = SubRegClass->EnumValue + 1;
1544         OS << "      " << EnumValue << ",\t// " << RC.getName() << ':'
1582           return std::pair(*LHS->getBaseClassOrder(), LHS->EnumValue) <
1583                  std::pair(*RHS->getBaseClassOrder(), RHS->EnumValue);
1852       if (!SubClasses.test(SRC.EnumValue))