Lines Matching defs:SchedRW

208   // Instantiate a CodeGenSchedClass for each unique SchedRW signature directly
213 // Sched and provide SchedRW list. This does not infer any new classes from
594 if (SchedDef->isValueUnset("SchedRW"))
596 for (const Record *RW : SchedDef->getValueAsListOfDefs("SchedRW")) {
743 // Call getSchedRWIdx for all elements in a sequence of SchedRW defs.
755 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead);
756 if (!SchedRW.IsSequence) {
760 int Repeat = SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1;
762 for (unsigned I : SchedRW.Sequence) {
824 CodeGenSchedRW SchedRW(RWIdx, IsRead, Seq, genRWName(Seq, IsRead));
825 RWVec.push_back(SchedRW);
840 // SchedRW list.
844 if (!Inst->TheDef->isValueUnset("SchedRW"))
845 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
891 dbgs() << "SchedRW machine model for " << InstName;
1007 // determined from ItinDef or SchedRW.
1307 void getIntersectingVariants(const CodeGenSchedRW &SchedRW, unsigned TransIdx,
1318 // All predicates associated with a given SchedRW are considered mutually
1330 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(PC.RWIdx, PC.IsRead);
1331 assert(SchedRW.HasVariants && "PredCheck must refer to a SchedVariant");
1332 ConstRecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");
1381 // given SchedRW whose processor indices and predicates are not mutually
1384 const CodeGenSchedRW &SchedRW, unsigned TransIdx,
1390 if (SchedRW.HasVariants) {
1392 if (SchedRW.TheDef->getValueInit("SchedModel")->isComplete()) {
1393 const Record *ModelDef = SchedRW.TheDef->getValueAsDef("SchedModel");
1399 SchedRW.TheDef->getValueAsListOfDefs("Variants"))
1400 Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0);
1405 for (ConstRecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
1433 Variants.emplace_back(AliasRW.TheDef, SchedRW.Index, AliasProcIdx, 0);
1460 PrintFatalError(SchedRW.TheDef->getLoc(),
1486 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(VInfo.RWIdx, IsRead);
1490 if (SchedRW.IsVariadic) {
1534 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(RWI, IsRead);
1543 getIntersectingVariants(SchedRW, TransIdx, IntersectingVariants);
1934 if (Inst->TheDef->isValueUnset("SchedRW")) {
2004 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead);
2005 if (SchedRW.TheDef) {
2006 if (!IsRead && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) {
2008 addWriteRes(SchedRW.TheDef, ProcModels[Idx]);
2009 } else if (IsRead && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) {
2011 addReadAdvance(SchedRW.TheDef, ProcModels[Idx]);
2014 for (auto *Alias : SchedRW.Aliases) {