Lines Matching defs:ProcIndices
837 SchedClasses.back().ProcIndices.push_back(0);
848 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/ {0});
877 if (SC.ProcIndices[0] != 0)
882 IdxVec ProcIndices;
884 ProcIndices.push_back(0);
889 ProcIndices.push_back(0);
902 ProcIndices.push_back(ProcModel.Index);
916 // If ProcIndices contains zero, the class applies to all processors.
918 if (!llvm::is_contained(ProcIndices, 0)) {
920 if (!llvm::is_contained(ProcIndices, PM.Index))
966 /// SchedWrites and SchedReads. ProcIndices contains the set of IDs of
971 ArrayRef<unsigned> ProcIndices) {
972 assert(!ProcIndices.empty() && "expect at least one ProcIdx");
983 std::set_union(SchedClasses[Idx].ProcIndices.begin(),
984 SchedClasses[Idx].ProcIndices.end(), ProcIndices.begin(),
985 ProcIndices.end(), std::back_inserter(PI));
986 SchedClasses[Idx].ProcIndices = std::move(PI);
996 SC.ProcIndices = ProcIndices;
1037 assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
1075 SC.ProcIndices.push_back(0);
1193 SchedClasses[Idx].ProcIndices);
1672 ArrayRef<unsigned> ProcIndices) {
1674 for (unsigned ProcId : ProcIndices) {
1688 ArrayRef<unsigned> ProcIndices) {
1689 LLVM_DEBUG(dbgs() << "INFER RW proc("; dumpIdxVec(ProcIndices);
1715 LastTransitions[0], llvm::is_contained(ProcIndices, 0)
1717 : ProcIndices);
1731 // OperWrites, OperReads, or ProcIndices after calling inferFromTransitions.
1829 // with processor resources. Refer to the parent SchedClass's ProcIndices to
1847 collectRWResources(SC.Writes, SC.Reads, SC.ProcIndices);
2003 ArrayRef<unsigned> ProcIndices) {
2007 for (unsigned Idx : ProcIndices)
2010 for (unsigned Idx : ProcIndices)
2020 AliasProcIndices = ProcIndices;
2035 ArrayRef<unsigned> ProcIndices) {
2037 collectRWResources(Idx, /*IsRead=*/false, ProcIndices);
2040 collectRWResources(Idx, /*IsRead=*/true, ProcIndices);
2215 dumpIdxVec(ProcIndices);