Lines Matching defs:Op0
107 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT);
112 EXPECT_TRUE(sd_match(Op0, m_SpecificVT(Int32VT)));
116 EXPECT_TRUE(sd_match(Op0, m_IntegerVT()));
153 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT);
157 SDValue ICMP_UGT = DAG->getSetCC(DL, MVT::i1, Op0, Op1, ISD::SETUGT);
158 SDValue ICMP_EQ01 = DAG->getSetCC(DL, MVT::i1, Op0, Op1, ISD::SETEQ);
159 SDValue ICMP_EQ10 = DAG->getSetCC(DL, MVT::i1, Op1, Op0, ISD::SETEQ);
191 EXPECT_TRUE(sd_match(ICMP_EQ01, m_SetCC(m_Specific(Op0), m_Specific(Op1),
193 EXPECT_TRUE(sd_match(ICMP_EQ10, m_SetCC(m_Specific(Op1), m_Specific(Op0),
195 EXPECT_FALSE(sd_match(ICMP_EQ01, m_SetCC(m_Specific(Op1), m_Specific(Op0),
197 EXPECT_FALSE(sd_match(ICMP_EQ10, m_SetCC(m_Specific(Op0), m_Specific(Op1),
199 EXPECT_TRUE(sd_match(ICMP_EQ01, m_c_SetCC(m_Specific(Op1), m_Specific(Op0),
201 EXPECT_TRUE(sd_match(ICMP_EQ10, m_c_SetCC(m_Specific(Op0), m_Specific(Op1),
208 EXPECT_FALSE(sd_match(ICMP_EQ01, m_Select(m_Specific(Op0), m_Specific(Op1),
246 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT);
252 SDValue Add = DAG->getNode(ISD::ADD, DL, Int32VT, Op0, Op1);
253 SDValue Sub = DAG->getNode(ISD::SUB, DL, Int32VT, Add, Op0);
255 SDValue And = DAG->getNode(ISD::AND, DL, Int32VT, Op0, Op1);
256 SDValue Xor = DAG->getNode(ISD::XOR, DL, Int32VT, Op1, Op0);
257 SDValue Or = DAG->getNode(ISD::OR, DL, Int32VT, Op0, Op1);
259 DAG->getNode(ISD::OR, DL, Int32VT, Op0, Op3, SDNodeFlags::Disjoint);
260 SDValue SMax = DAG->getNode(ISD::SMAX, DL, Int32VT, Op0, Op1);
261 SDValue SMin = DAG->getNode(ISD::SMIN, DL, Int32VT, Op1, Op0);
262 SDValue UMax = DAG->getNode(ISD::UMAX, DL, Int32VT, Op0, Op1);
263 SDValue UMin = DAG->getNode(ISD::UMIN, DL, Int32VT, Op1, Op0);
264 SDValue Rotl = DAG->getNode(ISD::ROTL, DL, Int32VT, Op0, Op1);
265 SDValue Rotr = DAG->getNode(ISD::ROTR, DL, Int32VT, Op1, Op0);
267 SDValue ICMP_GT = DAG->getSetCC(DL, MVT::i1, Op0, Op1, ISD::SETGT);
268 SDValue ICMP_GE = DAG->getSetCC(DL, MVT::i1, Op0, Op1, ISD::SETGE);
269 SDValue ICMP_UGT = DAG->getSetCC(DL, MVT::i1, Op0, Op1, ISD::SETUGT);
270 SDValue ICMP_UGE = DAG->getSetCC(DL, MVT::i1, Op0, Op1, ISD::SETUGE);
271 SDValue ICMP_LT = DAG->getSetCC(DL, MVT::i1, Op0, Op1, ISD::SETLT);
272 SDValue ICMP_LE = DAG->getSetCC(DL, MVT::i1, Op0, Op1, ISD::SETLE);
273 SDValue ICMP_ULT = DAG->getSetCC(DL, MVT::i1, Op0, Op1, ISD::SETULT);
274 SDValue ICMP_ULE = DAG->getSetCC(DL, MVT::i1, Op0, Op1, ISD::SETULE);
275 SDValue SMaxLikeGT = DAG->getSelect(DL, MVT::i32, ICMP_GT, Op0, Op1);
276 SDValue SMaxLikeGE = DAG->getSelect(DL, MVT::i32, ICMP_GE, Op0, Op1);
277 SDValue UMaxLikeUGT = DAG->getSelect(DL, MVT::i32, ICMP_UGT, Op0, Op1);
278 SDValue UMaxLikeUGE = DAG->getSelect(DL, MVT::i32, ICMP_UGE, Op0, Op1);
279 SDValue SMinLikeLT = DAG->getSelect(DL, MVT::i32, ICMP_LT, Op0, Op1);
280 SDValue SMinLikeLE = DAG->getSelect(DL, MVT::i32, ICMP_LE, Op0, Op1);
281 SDValue UMinLikeULT = DAG->getSelect(DL, MVT::i32, ICMP_ULT, Op0, Op1);
282 SDValue UMinLikeULE = DAG->getSelect(DL, MVT::i32, ICMP_ULE, Op0, Op1);
292 DAG->getNode(ISD::INSERT_VECTOR_ELT, DL, VInt32VT, V1, Op0, Op4);
375 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT);
380 SDValue ZExt = DAG->getNode(ISD::ZERO_EXTEND, DL, Int64VT, Op0);
383 SDValue SExt = DAG->getNode(ISD::SIGN_EXTEND, DL, Int64VT, Op0);
386 SDValue Sub = DAG->getNode(ISD::SUB, DL, Int32VT, Trunc, Op0);
387 SDValue Neg = DAG->getNegative(Op0, DL, Int32VT);
388 SDValue Not = DAG->getNOT(DL, Op0, Int32VT);
395 SDValue Bcast = DAG->getNode(ISD::BITCAST, DL, FloatVT, Op0);
396 SDValue Brev = DAG->getNode(ISD::BITREVERSE, DL, Int32VT, Op0);
397 SDValue Bswap = DAG->getNode(ISD::BSWAP, DL, Int32VT, Op0);
399 SDValue Ctpop = DAG->getNode(ISD::CTPOP, DL, Int32VT, Op0);
400 SDValue Ctlz = DAG->getNode(ISD::CTLZ, DL, Int32VT, Op0);
401 SDValue Cttz = DAG->getNode(ISD::CTTZ, DL, Int32VT, Op0);
493 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT);
496 SDValue Add = DAG->getNode(ISD::ADD, DL, Int32VT, Op0, Op1);
497 SDValue Sub = DAG->getNode(ISD::SUB, DL, Int32VT, Add, Op0);
542 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT);
545 SDValue Add = DAG->getNode(ISD::ADD, DL, Int32VT, Op0, Op1);
643 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int64VT);
646 SDValue Add = DAG->getNode(ISD::ADD, DL, Int64VT, Op0, Op0);
649 EXPECT_TRUE(sd_match(Op0, DAG.get(), m_LegalType(m_Value())));