Lines Matching defs:fpu

9473 static void Print_x86_float_state_t(MachO::x86_float_state64_t &fpu) {
9474   outs() << "\t    fpu_reserved[0] " << fpu.fpu_reserved[0];
9475   outs() << " fpu_reserved[1] " << fpu.fpu_reserved[1] << "\n";
9476   outs() << "\t    control: invalid " << fpu.fpu_fcw.invalid;
9477   outs() << " denorm " << fpu.fpu_fcw.denorm;
9478   outs() << " zdiv " << fpu.fpu_fcw.zdiv;
9479   outs() << " ovrfl " << fpu.fpu_fcw.ovrfl;
9480   outs() << " undfl " << fpu.fpu_fcw.undfl;
9481   outs() << " precis " << fpu.fpu_fcw.precis << "\n";
9483   if (fpu.fpu_fcw.pc == MachO::x86_FP_PREC_24B)
9485   else if (fpu.fpu_fcw.pc == MachO::x86_FP_PREC_53B)
9487   else if (fpu.fpu_fcw.pc == MachO::x86_FP_PREC_64B)
9490     outs() << fpu.fpu_fcw.pc << " ";
9492   if (fpu.fpu_fcw.rc == MachO::x86_FP_RND_NEAR)
9494   else if (fpu.fpu_fcw.rc == MachO::x86_FP_RND_DOWN)
9496   else if (fpu.fpu_fcw.rc == MachO::x86_FP_RND_UP)
9498   else if (fpu.fpu_fcw.rc == MachO::x86_FP_CHOP)
9501   outs() << "\t    status: invalid " << fpu.fpu_fsw.invalid;
9502   outs() << " denorm " << fpu.fpu_fsw.denorm;
9503   outs() << " zdiv " << fpu.fpu_fsw.zdiv;
9504   outs() << " ovrfl " << fpu.fpu_fsw.ovrfl;
9505   outs() << " undfl " << fpu.fpu_fsw.undfl;
9506   outs() << " precis " << fpu.fpu_fsw.precis;
9507   outs() << " stkflt " << fpu.fpu_fsw.stkflt << "\n";
9508   outs() << "\t            errsumm " << fpu.fpu_fsw.errsumm;
9509   outs() << " c0 " << fpu.fpu_fsw.c0;
9510   outs() << " c1 " << fpu.fpu_fsw.c1;
9511   outs() << " c2 " << fpu.fpu_fsw.c2;
9512   outs() << " tos " << fpu.fpu_fsw.tos;
9513   outs() << " c3 " << fpu.fpu_fsw.c3;
9514   outs() << " busy " << fpu.fpu_fsw.busy << "\n";
9515   outs() << "\t    fpu_ftw " << format("0x%02" PRIx32, fpu.fpu_ftw);
9516   outs() << " fpu_rsrv1 " << format("0x%02" PRIx32, fpu.fpu_rsrv1);
9517   outs() << " fpu_fop " << format("0x%04" PRIx32, fpu.fpu_fop);
9518   outs() << " fpu_ip " << format("0x%08" PRIx32, fpu.fpu_ip) << "\n";
9519   outs() << "\t    fpu_cs " << format("0x%04" PRIx32, fpu.fpu_cs);
9520   outs() << " fpu_rsrv2 " << format("0x%04" PRIx32, fpu.fpu_rsrv2);
9521   outs() << " fpu_dp " << format("0x%08" PRIx32, fpu.fpu_dp);
9522   outs() << " fpu_ds " << format("0x%04" PRIx32, fpu.fpu_ds) << "\n";
9523   outs() << "\t    fpu_rsrv3 " << format("0x%04" PRIx32, fpu.fpu_rsrv3);
9524   outs() << " fpu_mxcsr " << format("0x%08" PRIx32, fpu.fpu_mxcsr);
9525   outs() << " fpu_mxcsrmask " << format("0x%08" PRIx32, fpu.fpu_mxcsrmask);
9528   Print_mmst_reg(fpu.fpu_stmm0);
9530   Print_mmst_reg(fpu.fpu_stmm1);
9532   Print_mmst_reg(fpu.fpu_stmm2);
9534   Print_mmst_reg(fpu.fpu_stmm3);
9536   Print_mmst_reg(fpu.fpu_stmm4);
9538   Print_mmst_reg(fpu.fpu_stmm5);
9540   Print_mmst_reg(fpu.fpu_stmm6);
9542   Print_mmst_reg(fpu.fpu_stmm7);
9544   Print_xmm_reg(fpu.fpu_xmm0);
9546   Print_xmm_reg(fpu.fpu_xmm1);
9548   Print_xmm_reg(fpu.fpu_xmm2);
9550   Print_xmm_reg(fpu.fpu_xmm3);
9552   Print_xmm_reg(fpu.fpu_xmm4);
9554   Print_xmm_reg(fpu.fpu_xmm5);
9556   Print_xmm_reg(fpu.fpu_xmm6);
9558   Print_xmm_reg(fpu.fpu_xmm7);
9560   Print_xmm_reg(fpu.fpu_xmm8);
9562   Print_xmm_reg(fpu.fpu_xmm9);
9564   Print_xmm_reg(fpu.fpu_xmm10);
9566   Print_xmm_reg(fpu.fpu_xmm11);
9568   Print_xmm_reg(fpu.fpu_xmm12);
9570   Print_xmm_reg(fpu.fpu_xmm13);
9572   Print_xmm_reg(fpu.fpu_xmm14);
9574   Print_xmm_reg(fpu.fpu_xmm15);
9579       outs() << format("%02" PRIx32, fpu.fpu_rsrv4[f * g]) << " ";
9582   outs() << "\t    fpu_reserved1 " << format("0x%08" PRIx32, fpu.fpu_reserved1);