Lines Matching +full:1 +full:- +full:d
2 # RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false -noalias=false …
3 # RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false -noalias=false …
4 # RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false -noalias=false …
12 st1 {v0.d}[0], [sp]
13 st1 {v0.2d}, [sp]
14 st1 {v0.2d, v1.2d}, [sp]
15 st1 {v0.2d, v1.2d, v2.2d}, [sp]
16 st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]
24 st1 {v0.d}[0], [sp], #8
25 st1 {v0.2d}, [sp], #16
26 st1 {v0.2d, v1.2d}, [sp], #32
27 st1 {v0.2d, v1.2d, v2.2d}, [sp], #48
28 st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #64
36 st1 {v0.d}[0], [sp], x0
37 st1 {v0.2d}, [sp], x0
38 st1 {v0.2d, v1.2d}, [sp], x0
39 st1 {v0.2d, v1.2d, v2.2d}, [sp], x0
40 st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], x0
43 # ALL-NEXT: Instructions: 3000
45 # M3-NEXT: Total Cycles: 10203
46 # M3-NEXT: Total uOps: 8400
48 # M4-NEXT: Total Cycles: 6603
49 # M4-NEXT: Total uOps: 8600
51 # M5-NEXT: Total Cycles: 6603
52 # M5-NEXT: Total uOps: 8600
56 # M3-NEXT: uOps Per Cycle: 0.82
57 # M3-NEXT: IPC: 0.29
58 # M3-NEXT: Block RThroughput: 72.0
60 # M4-NEXT: uOps Per Cycle: 1.30
61 # M4-NEXT: IPC: 0.45
62 # M4-NEXT: Block RThroughput: 33.0
64 # M5-NEXT: uOps Per Cycle: 1.30
65 # M5-NEXT: IPC: 0.45
66 # M5-NEXT: Block RThroughput: 33.0
69 # ALL-NEXT: [1]: #uOps
70 # ALL-NEXT: [2]: Latency
71 # ALL-NEXT: [3]: RThroughput
72 # ALL-NEXT: [4]: MayLoad
73 # ALL-NEXT: [5]: MayStore
74 # ALL-NEXT: [6]: HasSideEffects (U)
76 # ALL: [1] [2] [3] [4] [5] [6] Instructions:
78 # M3-NEXT: 4 7 3.00 * st1 { v0.s }[0], [sp]
79 # M3-NEXT: 1 1 1.00 * st1 { v0.2s }, [sp]
80 # M3-NEXT: 2 2 2.00 * st1 { v0.2s, v1.2s }, [sp]
81 # M3-NEXT: 3 3 3.00 * st1 { v0.2s, v1.2s, v2.2s }, [sp]
82 # M3-NEXT: 4 4 4.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
83 # M3-NEXT: 4 7 3.00 * st1 { v0.d }[0], [sp]
84 # M3-NEXT: 1 1 1.00 * st1 { v0.2d }, [sp]
85 # M3-NEXT: 2 2 2.00 * st1 { v0.2d, v1.2d }, [sp]
86 # M3-NEXT: 3 3 3.00 * st1 { v0.2d, v1.2d, v2.2d }, [sp]
87 # M3-NEXT: 4 4 4.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
88 # M3-NEXT: 4 7 3.00 * st1 { v0.s }[0], [sp], #4
89 # M3-NEXT: 1 1 1.00 * st1 { v0.2s }, [sp], #8
90 # M3-NEXT: 2 2 2.00 * st1 { v0.2s, v1.2s }, [sp], #16
91 # M3-NEXT: 3 3 3.00 * st1 { v0.2s, v1.2s, v2.2s }, [sp], #24
92 # M3-NEXT: 4 4 4.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32
93 # M3-NEXT: 4 7 3.00 * st1 { v0.d }[0], [sp], #8
94 # M3-NEXT: 1 1 1.00 * st1 { v0.2d }, [sp], #16
95 # M3-NEXT: 2 2 2.00 * st1 { v0.2d, v1.2d }, [sp], #32
96 # M3-NEXT: 3 3 3.00 * st1 { v0.2d, v1.2d, v2.2d }, [sp], #48
97 # M3-NEXT: 4 4 4.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64
98 # M3-NEXT: 4 7 3.00 * st1 { v0.s }[0], [sp], x0
99 # M3-NEXT: 1 1 1.00 * st1 { v0.2s }, [sp], x0
100 # M3-NEXT: 2 2 2.00 * st1 { v0.2s, v1.2s }, [sp], x0
101 # M3-NEXT: 3 3 3.00 * st1 { v0.2s, v1.2s, v2.2s }, [sp], x0
102 # M3-NEXT: 4 4 4.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
103 # M3-NEXT: 4 7 3.00 * st1 { v0.d }[0], [sp], x0
104 # M3-NEXT: 1 1 1.00 * st1 { v0.2d }, [sp], x0
105 # M3-NEXT: 2 2 2.00 * st1 { v0.2d, v1.2d }, [sp], x0
106 # M3-NEXT: 3 3 3.00 * st1 { v0.2d, v1.2d, v2.2d }, [sp], x0
107 # M3-NEXT: 4 4 4.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0
109 # M4-NEXT: 1 1 0.50 * st1 { v0.s }[0], [sp]
110 # M4-NEXT: 1 1 0.50 * st1 { v0.2s }, [sp]
111 # M4-NEXT: 2 2 1.00 * st1 { v0.2s, v1.2s }, [sp]
112 # M4-NEXT: 3 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp]
113 # M4-NEXT: 4 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
114 # M4-NEXT: 1 1 0.50 * st1 { v0.d }[0], [sp]
115 # M4-NEXT: 1 1 0.50 * st1 { v0.2d }, [sp]
116 # M4-NEXT: 2 2 1.00 * st1 { v0.2d, v1.2d }, [sp]
117 # M4-NEXT: 3 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp]
118 # M4-NEXT: 4 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
119 # M4-NEXT: 2 1 0.50 * st1 { v0.s }[0], [sp], #4
120 # M4-NEXT: 2 1 0.50 * st1 { v0.2s }, [sp], #8
121 # M4-NEXT: 3 2 1.00 * st1 { v0.2s, v1.2s }, [sp], #16
122 # M4-NEXT: 4 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp], #24
123 # M4-NEXT: 5 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32
124 # M4-NEXT: 2 1 0.50 * st1 { v0.d }[0], [sp], #8
125 # M4-NEXT: 2 1 0.50 * st1 { v0.2d }, [sp], #16
126 # M4-NEXT: 3 2 1.00 * st1 { v0.2d, v1.2d }, [sp], #32
127 # M4-NEXT: 4 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp], #48
128 # M4-NEXT: 5 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64
129 # M4-NEXT: 2 1 0.50 * st1 { v0.s }[0], [sp], x0
130 # M4-NEXT: 2 1 0.50 * st1 { v0.2s }, [sp], x0
131 # M4-NEXT: 3 2 1.00 * st1 { v0.2s, v1.2s }, [sp], x0
132 # M4-NEXT: 4 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp], x0
133 # M4-NEXT: 5 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
134 # M4-NEXT: 2 1 0.50 * st1 { v0.d }[0], [sp], x0
135 # M4-NEXT: 2 1 0.50 * st1 { v0.2d }, [sp], x0
136 # M4-NEXT: 3 2 1.00 * st1 { v0.2d, v1.2d }, [sp], x0
137 # M4-NEXT: 4 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp], x0
138 # M4-NEXT: 5 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0
140 # M5-NEXT: 1 1 0.50 * st1 { v0.s }[0], [sp]
141 # M5-NEXT: 1 1 0.50 * st1 { v0.2s }, [sp]
142 # M5-NEXT: 2 2 1.00 * st1 { v0.2s, v1.2s }, [sp]
143 # M5-NEXT: 3 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp]
144 # M5-NEXT: 4 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
145 # M5-NEXT: 1 1 0.50 * st1 { v0.d }[0], [sp]
146 # M5-NEXT: 1 1 0.50 * st1 { v0.2d }, [sp]
147 # M5-NEXT: 2 2 1.00 * st1 { v0.2d, v1.2d }, [sp]
148 # M5-NEXT: 3 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp]
149 # M5-NEXT: 4 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
150 # M5-NEXT: 2 1 0.50 * st1 { v0.s }[0], [sp], #4
151 # M5-NEXT: 2 1 0.50 * st1 { v0.2s }, [sp], #8
152 # M5-NEXT: 3 2 1.00 * st1 { v0.2s, v1.2s }, [sp], #16
153 # M5-NEXT: 4 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp], #24
154 # M5-NEXT: 5 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32
155 # M5-NEXT: 2 1 0.50 * st1 { v0.d }[0], [sp], #8
156 # M5-NEXT: 2 1 0.50 * st1 { v0.2d }, [sp], #16
157 # M5-NEXT: 3 2 1.00 * st1 { v0.2d, v1.2d }, [sp], #32
158 # M5-NEXT: 4 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp], #48
159 # M5-NEXT: 5 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64
160 # M5-NEXT: 2 1 0.50 * st1 { v0.s }[0], [sp], x0
161 # M5-NEXT: 2 1 0.50 * st1 { v0.2s }, [sp], x0
162 # M5-NEXT: 3 2 1.00 * st1 { v0.2s, v1.2s }, [sp], x0
163 # M5-NEXT: 4 3 1.50 * st1 { v0.2s, v1.2s, v2.2s }, [sp], x0
164 # M5-NEXT: 5 4 2.00 * st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
165 # M5-NEXT: 2 1 0.50 * st1 { v0.d }[0], [sp], x0
166 # M5-NEXT: 2 1 0.50 * st1 { v0.2d }, [sp], x0
167 # M5-NEXT: 3 2 1.00 * st1 { v0.2d, v1.2d }, [sp], x0
168 # M5-NEXT: 4 3 1.50 * st1 { v0.2d, v1.2d, v2.2d }, [sp], x0
169 # M5-NEXT: 5 4 2.00 * st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0