Lines Matching full:same
11 ; SVML-SAME: [6 x ptr] [
12 ; SVML-SAME: ptr @__svml_sin2,
13 ; SVML-SAME: ptr @__svml_sin4,
14 ; SVML-SAME: ptr @__svml_sin8,
15 ; SVML-SAME: ptr @__svml_log10f4,
16 ; SVML-SAME: ptr @__svml_log10f8,
17 ; SVML-SAME: ptr @__svml_log10f16
18 ; AMDLIBM-SAME: [11 x ptr] [
19 ; AMDLIBM-SAME: ptr @amd_vrd2_sin,
20 ; AMDLIBM-SAME: ptr @amd_vrd4_sin,
21 ; AMDLIBM-SAME: ptr @amd_vrd8_sin,
22 ; AMDLIBM-SAME: ptr @amd_vrd4_sincos,
23 ; AMDLIBM-SAME: ptr @amd_vrd8_sincos,
24 ; AMDLIBM-SAME: ptr @amd_vrs4_sincosf,
25 ; AMDLIBM-SAME: ptr @amd_vrs8_sincosf,
26 ; AMDLIBM-SAME: ptr @amd_vrs16_sincosf
27 ; AMDLIBM-SAME: ptr @amd_vrs4_log10f,
28 ; AMDLIBM-SAME: ptr @amd_vrs8_log10f,
29 ; AMDLIBM-SAME: ptr @amd_vrs16_log10f
30 ; MASSV-SAME: [2 x ptr] [
31 ; MASSV-SAME: ptr @__sind2,
32 ; MASSV-SAME: ptr @__log10f4
33 ; ACCELERATE-SAME: [1 x ptr] [
34 ; ACCELERATE-SAME: ptr @vlog10f
35 ; LIBMVEC-X86-SAME: [2 x ptr] [
36 ; LIBMVEC-X86-SAME: ptr @_ZGVbN2v_sin,
37 ; LIBMVEC-X86-SAME: ptr @_ZGVdN4v_sin
38 ; SLEEFGNUABI-SAME: [16 x ptr] [
39 ; SLEEFGNUABI-SAME: ptr @_ZGVnN2vl8_modf,
40 ; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl8_modf,
41 ; SLEEFGNUABI-SAME: ptr @_ZGVnN4vl4_modff,
42 ; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl4_modff,
43 ; SLEEFGNUABI-SAME: ptr @_ZGVnN2v_sin,
44 ; SLEEFGNUABI-SAME: ptr @_ZGVsMxv_sin,
45 ; SLEEFGNUABI-SAME: ptr @_ZGVnN2vl8l8_sincos,
46 ; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl8l8_sincos,
47 ; SLEEFGNUABI-SAME: ptr @_ZGVnN4vl4l4_sincosf,
48 ; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl4l4_sincosf,
49 ; SLEEFGNUABI-SAME: ptr @_ZGVnN2vl8l8_sincospi,
50 ; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl8l8_sincospi,
51 ; SLEEFGNUABI-SAME: ptr @_ZGVnN4vl4l4_sincospif,
52 ; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl4l4_sincospif,
54 ; SLEEFGNUABI-SAME: ptr @_ZGVsMxv_log10f
55 ; ARMPL-SAME: [16 x ptr] [
56 ; ARMPL-SAME: ptr @armpl_vmodfq_f64,
57 ; ARMPL-SAME: ptr @armpl_svmodf_f64_x,
58 ; ARMPL-SAME: ptr @armpl_vmodfq_f32,
59 ; ARMPL-SAME: ptr @armpl_svmodf_f32_x,
60 ; ARMPL-SAME: ptr @armpl_vsinq_f64,
61 ; ARMPL-SAME: ptr @armpl_svsin_f64_x,
62 ; ARMPL-SAME: ptr @armpl_vsincosq_f64,
63 ; ARMPL-SAME: ptr @armpl_svsincos_f64_x,
64 ; ARMPL-SAME: ptr @armpl_vsincosq_f32,
65 ; ARMPL-SAME: ptr @armpl_svsincos_f32_x,
66 ; ARMPL-SAME: ptr @armpl_vsincospiq_f64,
67 ; ARMPL-SAME: ptr @armpl_svsincospi_f64_x,
68 ; ARMPL-SAME: ptr @armpl_vsincospiq_f32,
69 ; ARMPL-SAME: ptr @armpl_svsincospi_f32_x,
70 ; ARMPL-SAME: ptr @armpl_vlog10q_f32,
71 ; ARMPL-SAME: ptr @armpl_svlog10_f32_x
72 ; COMMON-SAME: ], section "llvm.metadata"
241 ; SVML-SAME: "_ZGV_LLVM_N2v_sin(__svml_sin2),
242 ; SVML-SAME: _ZGV_LLVM_N4v_sin(__svml_sin4),
243 ; SVML-SAME: _ZGV_LLVM_N8v_sin(__svml_sin8)" }
246 ; AMDLIBM-SAME: "_ZGV_LLVM_N2v_sin(amd_vrd2_sin),
247 ; AMDLIBM-SAME: _ZGV_LLVM_N4v_sin(amd_vrd4_sin),
248 ; AMDLIBM-SAME: _ZGV_LLVM_N8v_sin(amd_vrd8_sin)" }
250 ; AMDLIBM-SAME: "_ZGV_LLVM_N4vl8l8_sincos(amd_vrd4_sincos),
251 ; AMDLIBM-SAME: _ZGV_LLVM_N8vl8l8_sincos(amd_vrd8_sincos)" }
253 ; AMDLIBM-SAME: "_ZGV_LLVM_N4vl4l4_sincosf(amd_vrs4_sincosf),
254 ; AMDLIBM-SAME: _ZGV_LLVM_N8vl4l4_sincosf(amd_vrs8_sincosf),
255 ; AMDLIBM-SAME: _ZGV_LLVM_N16vl4l4_sincosf(amd_vrs16_sincosf)" }
257 ; AMDLIBM-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(amd_vrs4_log10f),
258 ; AMDLIBM-SAME: _ZGV_LLVM_N8v_llvm.log10.f32(amd_vrs8_log10f),
259 ; AMDLIBM-SAME: _ZGV_LLVM_N16v_llvm.log10.f32(amd_vrs16_log10f)" }
262 ; MASSV-SAME: "_ZGV_LLVM_N2v_sin(__sind2)" }
264 ; MASSV-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(__log10f4)" }
267 ; ACCELERATE-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(vlog10f)" }
270 ; LIBMVEC-X86-SAME: "_ZGV_LLVM_N2v_sin(_ZGVbN2v_sin),
271 ; LIBMVEC-X86-SAME: _ZGV_LLVM_N4v_sin(_ZGVdN4v_sin)" }
274 ; SLEEFGNUABI-SAME: "_ZGV_LLVM_N2vl8_modf(_ZGVnN2vl8_modf),
275 ; SLEEFGNUABI-SAME: _ZGVsNxvl8_modf(_ZGVsNxvl8_modf)" }
277 ; SLEEFGNUABI-SAME: "_ZGV_LLVM_N4vl4_modff(_ZGVnN4vl4_modff),
278 ; SLEEFGNUABI-SAME: _ZGVsNxvl4_modff(_ZGVsNxvl4_modff)" }
280 ; SLEEFGNUABI-SAME: "_ZGV_LLVM_N2v_sin(_ZGVnN2v_sin),
281 ; SLEEFGNUABI-SAME: _ZGVsMxv_sin(_ZGVsMxv_sin)" }
283 ; SLEEFGNUABI-SAME: "_ZGV_LLVM_N2vl8l8_sincos(_ZGVnN2vl8l8_sincos),
284 ; SLEEFGNUABI-SAME: _ZGVsNxvl8l8_sincos(_ZGVsNxvl8l8_sincos)" }
286 ; SLEEFGNUABI-SAME: "_ZGV_LLVM_N4vl4l4_sincosf(_ZGVnN4vl4l4_sincosf),
287 ; SLEEFGNUABI-SAME: _ZGVsNxvl4l4_sincosf(_ZGVsNxvl4l4_sincosf)" }
289 ; SLEEFGNUABI-SAME: "_ZGV_LLVM_N2vl8l8_sincospi(_ZGVnN2vl8l8_sincospi),
290 ; SLEEFGNUABI-SAME: _ZGVsNxvl8l8_sincospi(_ZGVsNxvl8l8_sincospi)" }
292 ; SLEEFGNUABI-SAME: "_ZGV_LLVM_N4vl4l4_sincospif(_ZGVnN4vl4l4_sincospif),
293 ; SLEEFGNUABI-SAME: _ZGVsNxvl4l4_sincospif(_ZGVsNxvl4l4_sincospif)" }
295 ; SLEEFGNUABI-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(_ZGVnN4v_log10f),
296 ; SLEEFGNUABI-SAME: _ZGVsMxv_llvm.log10.f32(_ZGVsMxv_log10f)" }
299 ; SLEEFGNUABI_RISCV-SAME: "_ZGVrNxv_sin(Sleef_sindx_u10rvvm2)" }
301 ; SLEEFGNUABI_RISCV-SAME: "_ZGVrNxv_llvm.log10.f32(Sleef_log10fx_u10rvvm2)" }
304 ; ARMPL-SAME: "_ZGV_LLVM_N2vl8_modf(armpl_vmodfq_f64),
305 ; ARMPL-SAME: _ZGVsMxvl8_modf(armpl_svmodf_f64_x)" }
307 ; ARMPL-SAME: "_ZGV_LLVM_N4vl4_modff(armpl_vmodfq_f32),
308 ; ARMPL-SAME: _ZGVsMxvl4_modff(armpl_svmodf_f32_x)" }
310 ; ARMPL-SAME: "_ZGV_LLVM_N2v_sin(armpl_vsinq_f64),
311 ; ARMPL-SAME: _ZGVsMxv_sin(armpl_svsin_f64_x)" }
313 ; ARMPL-SAME: "_ZGV_LLVM_N2vl8l8_sincos(armpl_vsincosq_f64),
314 ; ARMPL-SAME: _ZGVsMxvl8l8_sincos(armpl_svsincos_f64_x)" }
316 ; ARMPL-SAME: "_ZGV_LLVM_N4vl4l4_sincosf(armpl_vsincosq_f32),
317 ; ARMPL-SAME: _ZGVsMxvl4l4_sincosf(armpl_svsincos_f32_x)" }
319 ; ARMPL-SAME: "_ZGV_LLVM_N2vl8l8_sincospi(armpl_vsincospiq_f64),
320 ; ARMPL-SAME: _ZGVsMxvl8l8_sincospi(armpl_svsincospi_f64_x)" }
322 ; ARMPL-SAME: "_ZGV_LLVM_N4vl4l4_sincospif(armpl_vsincospiq_f32),
323 ; ARMPL-SAME: _ZGVsMxvl4l4_sincospif(armpl_svsincospi_f32_x)" }
325 ; ARMPL-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(armpl_vlog10q_f32),
326 ; ARMPL-SAME: _ZGVsMxv_llvm.log10.f32(armpl_svlog10_f32_x)" }