Lines Matching full:accesses

2 …force-vector-width=8 -force-vector-interleave=1 -enable-interleaved-mem-accesses -debug-only=loop-…
3 … -force-vector-interleave=1 -enable-interleaved-mem-accesses -enable-masked-interleaved-mem-access…
8 ; predicated memory accesses only if they are both in the same (predicated)
10 ; If the accesses are not in the same predicated block, an interleave-group
34 ; STRIDED_UNMASKED: LV: Analyzing interleaved accesses...
38 ; STRIDED_MASKED: LV: Analyzing interleaved accesses...
49 ; stores (if masked-interleaved-accesses are enabled).
50 ; If masked-interleaved-accesses is not enabled we create only one interleave
67 ; STRIDED_UNMASKED: LV: Analyzing interleaved accesses...
73 ; STRIDED_MASKED: LV: Analyzing interleaved accesses...
80 ; group because the two accesses are in separate predicated blocks.
81 ; We therefore create a separate interleave-group with gaps for each of the accesses,
82 ; If masked-interleaved-accesses is not enabled we don't create any interleave
83 ; group because all accesses are predicated.
101 ; STRIDED_UNMASKED: LV: Analyzing interleaved accesses...
105 ; STRIDED_MASKED: LV: Analyzing interleaved accesses...