Lines Matching full:mul

13   %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
14   ret <4 x i8> %mul
23   %mul = mul <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
24   ret <4 x i8> %mul
30 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], splat (i8 1)
31 ; CHECK-NEXT:    ret <4 x i8> [[MUL]]
34   %mul = mul <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
35   ret <4 x i8> %mul
41 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], splat (i8 2)
42 ; CHECK-NEXT:    ret <4 x i8> [[MUL]]
45   %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 4, i8 4>
46   ret <4 x i8> %mul
52 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], splat (i8 3)
53 ; CHECK-NEXT:    ret <4 x i8> [[MUL]]
56   %mul = mul <4 x i8> %InVec, <i8 8, i8 8, i8 8, i8 8>
57   ret <4 x i8> %mul
63 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], <i8 0, i8 1, i8 2, i8 3>
64 ; CHECK-NEXT:    ret <4 x i8> [[MUL]]
67   %mul = mul <4 x i8> %InVec, <i8 1, i8 2, i8 4, i8 8>
68   ret <4 x i8> %mul
74 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i8> [[INVEC:%.*]], splat (i8 3)
75 ; CHECK-NEXT:    ret <4 x i8> [[MUL]]
78   %mul = mul <4 x i8> %InVec, <i8 3, i8 3, i8 3, i8 3>
79   ret <4 x i8> %mul
85 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], <i8 2, i8 2, i8 1, i8 1>
86 ; CHECK-NEXT:    ret <4 x i8> [[MUL]]
89   %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 2, i8 2>
90   ret <4 x i8> %mul
96 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i8> [[INVEC:%.*]], <i8 4, i8 4, i8 0, i8 1>
97 ; CHECK-NEXT:    ret <4 x i8> [[MUL]]
100   %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 0, i8 1>
101   ret <4 x i8> %mul
110   %mul = mul <4 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0>
111   ret <4 x i16> %mul
120   %mul = mul <4 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1>
121   ret <4 x i16> %mul
127 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i16> [[INVEC:%.*]], splat (i16 1)
128 ; CHECK-NEXT:    ret <4 x i16> [[MUL]]
131   %mul = mul <4 x i16> %InVec, <i16 2, i16 2, i16 2, i16 2>
132   ret <4 x i16> %mul
138 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i16> [[INVEC:%.*]], splat (i16 2)
139 ; CHECK-NEXT:    ret <4 x i16> [[MUL]]
142   %mul = mul <4 x i16> %InVec, <i16 4, i16 4, i16 4, i16 4>
143   ret <4 x i16> %mul
149 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i16> [[INVEC:%.*]], splat (i16 3)
150 ; CHECK-NEXT:    ret <4 x i16> [[MUL]]
153   %mul = mul <4 x i16> %InVec, <i16 8, i16 8, i16 8, i16 8>
154   ret <4 x i16> %mul
160 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i16> [[INVEC:%.*]], <i16 0, i16 1, i16 2, i16 3>
161 ; CHECK-NEXT:    ret <4 x i16> [[MUL]]
164   %mul = mul <4 x i16> %InVec, <i16 1, i16 2, i16 4, i16 8>
165   ret <4 x i16> %mul
171 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i16> [[INVEC:%.*]], splat (i16 3)
172 ; CHECK-NEXT:    ret <4 x i16> [[MUL]]
175   %mul = mul <4 x i16> %InVec, <i16 3, i16 3, i16 3, i16 3>
176   ret <4 x i16> %mul
182 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i16> [[INVEC:%.*]], <i16 2, i16 2, i16 1, i16 1>
183 ; CHECK-NEXT:    ret <4 x i16> [[MUL]]
186   %mul = mul <4 x i16> %InVec, <i16 4, i16 4, i16 2, i16 2>
187   ret <4 x i16> %mul
193 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i16> [[INVEC:%.*]], <i16 4, i16 4, i16 0, i16 2>
194 ; CHECK-NEXT:    ret <4 x i16> [[MUL]]
197   %mul = mul <4 x i16> %InVec, <i16 4, i16 4, i16 0, i16 2>
198   ret <4 x i16> %mul
207   %mul = mul <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
208   ret <4 x i32> %mul
217   %mul = mul <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
218   ret <4 x i32> %mul
224 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i32> [[INVEC:%.*]], splat (i32 1)
225 ; CHECK-NEXT:    ret <4 x i32> [[MUL]]
228   %mul = mul <4 x i32> %InVec, <i32 2, i32 2, i32 2, i32 2>
229   ret <4 x i32> %mul
235 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i32> [[INVEC:%.*]], splat (i32 2)
236 ; CHECK-NEXT:    ret <4 x i32> [[MUL]]
239   %mul = mul <4 x i32> %InVec, <i32 4, i32 4, i32 4, i32 4>
240   ret <4 x i32> %mul
246 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i32> [[INVEC:%.*]], splat (i32 3)
247 ; CHECK-NEXT:    ret <4 x i32> [[MUL]]
250   %mul = mul <4 x i32> %InVec, <i32 8, i32 8, i32 8, i32 8>
251   ret <4 x i32> %mul
257 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i32> [[INVEC:%.*]], <i32 0, i32 1, i32 2, i32 3>
258 ; CHECK-NEXT:    ret <4 x i32> [[MUL]]
261   %mul = mul <4 x i32> %InVec, <i32 1, i32 2, i32 4, i32 8>
262   ret <4 x i32> %mul
268 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i32> [[INVEC:%.*]], splat (i32 3)
269 ; CHECK-NEXT:    ret <4 x i32> [[MUL]]
272   %mul = mul <4 x i32> %InVec, <i32 3, i32 3, i32 3, i32 3>
273   ret <4 x i32> %mul
279 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i32> [[INVEC:%.*]], <i32 2, i32 2, i32 1, i32 1>
280 ; CHECK-NEXT:    ret <4 x i32> [[MUL]]
283   %mul = mul <4 x i32> %InVec, <i32 4, i32 4, i32 2, i32 2>
284   ret <4 x i32> %mul
290 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i32> [[INVEC:%.*]], <i32 4, i32 4, i32 0, i32 1>
291 ; CHECK-NEXT:    ret <4 x i32> [[MUL]]
294   %mul = mul <4 x i32> %InVec, <i32 4, i32 4, i32 0, i32 1>
295   ret <4 x i32> %mul
304   %mul = mul <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
305   ret <4 x i64> %mul
314   %mul = mul <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
315   ret <4 x i64> %mul
321 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i64> [[INVEC:%.*]], splat (i64 1)
322 ; CHECK-NEXT:    ret <4 x i64> [[MUL]]
325   %mul = mul <4 x i64> %InVec, <i64 2, i64 2, i64 2, i64 2>
326   ret <4 x i64> %mul
332 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i64> [[INVEC:%.*]], splat (i64 2)
333 ; CHECK-NEXT:    ret <4 x i64> [[MUL]]
336   %mul = mul <4 x i64> %InVec, <i64 4, i64 4, i64 4, i64 4>
337   ret <4 x i64> %mul
343 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i64> [[INVEC:%.*]], splat (i64 3)
344 ; CHECK-NEXT:    ret <4 x i64> [[MUL]]
347   %mul = mul <4 x i64> %InVec, <i64 8, i64 8, i64 8, i64 8>
348   ret <4 x i64> %mul
354 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i64> [[INVEC:%.*]], <i64 0, i64 1, i64 2, i64 3>
355 ; CHECK-NEXT:    ret <4 x i64> [[MUL]]
358   %mul = mul <4 x i64> %InVec, <i64 1, i64 2, i64 4, i64 8>
359   ret <4 x i64> %mul
365 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i64> [[INVEC:%.*]], splat (i64 3)
366 ; CHECK-NEXT:    ret <4 x i64> [[MUL]]
369   %mul = mul <4 x i64> %InVec, <i64 3, i64 3, i64 3, i64 3>
370   ret <4 x i64> %mul
376 ; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i64> [[INVEC:%.*]], <i64 2, i64 2, i64 1, i64 1>
377 ; CHECK-NEXT:    ret <4 x i64> [[MUL]]
380   %mul = mul <4 x i64> %InVec, <i64 4, i64 4, i64 2, i64 2>
381   ret <4 x i64> %mul
387 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i64> [[INVEC:%.*]], <i64 4, i64 4, i64 0, i64 1>
388 ; CHECK-NEXT:    ret <4 x i64> [[MUL]]
391   %mul = mul <4 x i64> %InVec, <i64 4, i64 4, i64 0, i64 1>
392   ret <4 x i64> %mul
402 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i8> [[INVEC:%.*]], splat (i8 12)
403 ; CHECK-NEXT:    ret <4 x i8> [[MUL]]
407   %mul = mul <4 x i8> %shl, <i8 3, i8 3, i8 3, i8 3>
408   ret <4 x i8> %mul
414 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i16> [[INVEC:%.*]], splat (i16 12)
415 ; CHECK-NEXT:    ret <4 x i16> [[MUL]]
419   %mul = mul <4 x i16> %shl, <i16 3, i16 3, i16 3, i16 3>
420   ret <4 x i16> %mul
426 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i32> [[INVEC:%.*]], splat (i32 12)
427 ; CHECK-NEXT:    ret <4 x i32> [[MUL]]
431   %mul = mul <4 x i32> %shl, <i32 3, i32 3, i32 3, i32 3>
432   ret <4 x i32> %mul
438 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i64> [[INVEC:%.*]], splat (i64 12)
439 ; CHECK-NEXT:    ret <4 x i64> [[MUL]]
443   %mul = mul <4 x i64> %shl, <i64 3, i64 3, i64 3, i64 3>
444   ret <4 x i64> %mul