Lines Matching full:arg
8 ; are uniform, i.e. %arg & 4294967168 can be either 4294967168 or 0
10 ; %t = add i32 %arg, 128
13 ; %t0 = shl i32 %arg, 24
15 ; %r = icmp eq i32 %t1, %arg
17 ; %t0 = trunc i32 %arg to i8
19 ; %r = icmp eq i32 %t1, %arg
24 ; %r = icmp sgt i32 %arg, -1
26 ; %t = and i32 %arg, 2147483648
33 ; %r = icmp ult i32 %arg, 128
39 define i1 @positive_with_signbit(i32 %arg) {
41 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
44 %t1 = icmp sgt i32 %arg, -1
45 %t2 = add i32 %arg, 128
51 define i1 @positive_with_signbit_logical(i32 %arg) {
53 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
56 %t1 = icmp sgt i32 %arg, -1
57 %t2 = add i32 %arg, 128
63 define i1 @positive_with_mask(i32 %arg) {
65 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
68 %t1 = and i32 %arg, 1107296256
70 %t3 = add i32 %arg, 128
76 define i1 @positive_with_mask_logical(i32 %arg) {
78 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
81 %t1 = and i32 %arg, 1107296256
83 %t3 = add i32 %arg, 128
89 define i1 @positive_with_icmp(i32 %arg) {
91 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
94 %t1 = icmp ult i32 %arg, 512
95 %t2 = add i32 %arg, 128
101 define i1 @positive_with_icmp_logical(i32 %arg) {
103 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
106 %t1 = icmp ult i32 %arg, 512
107 %t2 = add i32 %arg, 128
114 define i1 @positive_with_aggressive_icmp(i32 %arg) {
116 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
119 %t1 = icmp ult i32 %arg, 128
120 %t2 = add i32 %arg, 256
126 define i1 @positive_with_aggressive_icmp_logical(i32 %arg) {
128 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
131 %t1 = icmp ult i32 %arg, 128
132 %t2 = add i32 %arg, 256
142 define i1 @positive_with_extra_and(i32 %arg, i1 %z) {
144 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
148 %t1 = icmp sgt i32 %arg, -1
149 %t2 = add i32 %arg, 128
156 define i1 @positive_with_extra_and_logical(i32 %arg, i1 %z) {
158 ; CHECK-NEXT: [[DOTSIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
162 %t1 = icmp sgt i32 %arg, -1
163 %t2 = add i32 %arg, 128
174 define <2 x i1> @positive_vec_splat(<2 x i32> %arg) {
176 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult <2 x i32> [[ARG:%.*]], splat (i32 128)
179 %t1 = icmp sgt <2 x i32> %arg, <i32 -1, i32 -1>
180 %t2 = add <2 x i32> %arg, <i32 128, i32 128>
186 define <2 x i1> @positive_vec_nonsplat(<2 x i32> %arg) {
188 ; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[ARG:%.*]], splat (i32 -1)
189 ; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[ARG]], <i32 128, i32 256>
194 %t1 = icmp sgt <2 x i32> %arg, <i32 -1, i32 -1>
195 %t2 = add <2 x i32> %arg, <i32 128, i32 256>
201 define <3 x i1> @positive_vec_poison0(<3 x i32> %arg) {
203 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult <3 x i32> [[ARG:%.*]], splat (i32 128)
206 %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 poison, i32 -1>
207 %t2 = add <3 x i32> %arg, <i32 128, i32 128, i32 128>
213 define <3 x i1> @positive_vec_poison1(<3 x i32> %arg) {
215 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult <3 x i32> [[ARG:%.*]], splat (i32 128)
218 %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 -1, i32 -1>
219 %t2 = add <3 x i32> %arg, <i32 128, i32 poison, i32 128>
225 define <3 x i1> @positive_vec_poison2(<3 x i32> %arg) {
227 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult <3 x i32> [[ARG:%.*]], splat (i32 128)
230 %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 -1, i32 -1>
231 %t2 = add <3 x i32> %arg, <i32 128, i32 128, i32 128>
237 define <3 x i1> @positive_vec_poison3(<3 x i32> %arg) {
239 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult <3 x i32> [[ARG:%.*]], splat (i32 128)
242 %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 poison, i32 -1>
243 %t2 = add <3 x i32> %arg, <i32 128, i32 poison, i32 128>
249 define <3 x i1> @positive_vec_poison4(<3 x i32> %arg) {
251 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult <3 x i32> [[ARG:%.*]], splat (i32 128)
254 %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 poison, i32 -1>
255 %t2 = add <3 x i32> %arg, <i32 128, i32 128, i32 128>
261 define <3 x i1> @positive_vec_poison5(<3 x i32> %arg) {
263 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult <3 x i32> [[ARG:%.*]], splat (i32 128)
266 %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 -1, i32 -1>
267 %t2 = add <3 x i32> %arg, <i32 128, i32 poison, i32 128>
273 define <3 x i1> @positive_vec_poison6(<3 x i32> %arg) {
275 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult <3 x i32> [[ARG:%.*]], splat (i32 128)
278 %t1 = icmp sgt <3 x i32> %arg, <i32 -1, i32 poison, i32 -1>
279 %t2 = add <3 x i32> %arg, <i32 128, i32 poison, i32 128>
293 ; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
294 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
297 %arg = call i32 @gen32()
298 %t1 = icmp sgt i32 %arg, -1
299 %t2 = add i32 %arg, 128
307 ; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
308 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
311 %arg = call i32 @gen32()
312 %t1 = icmp sgt i32 %arg, -1
313 %t2 = add i32 %arg, 128
321 ; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
322 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
325 %arg = call i32 @gen32()
326 %t1 = icmp ult i32 %arg, 512
327 %t2 = add i32 %arg, 128
335 ; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
336 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
339 %arg = call i32 @gen32()
340 %t1 = icmp ult i32 %arg, 512
341 %t2 = add i32 %arg, 128
351 define i1 @positive_trunc_signbit(i32 %arg) {
353 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
356 %t1 = trunc i32 %arg to i8
358 %t3 = add i32 %arg, 128
364 define i1 @positive_trunc_signbit_logical(i32 %arg) {
366 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
369 %t1 = trunc i32 %arg to i8
371 %t3 = add i32 %arg, 128
377 define i1 @positive_trunc_base(i32 %arg) {
379 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 65408
383 %t1 = trunc i32 %arg to i16
391 define i1 @positive_trunc_base_logical(i32 %arg) {
393 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 65408
397 %t1 = trunc i32 %arg to i16
405 define i1 @positive_different_trunc_both(i32 %arg) {
407 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 16384
409 ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[ARG]] to i16
415 %t1 = trunc i32 %arg to i15
417 %t3 = trunc i32 %arg to i16
424 define i1 @positive_different_trunc_both_logical(i32 %arg) {
426 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 16384
428 ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[ARG]] to i16
434 %t1 = trunc i32 %arg to i15
436 %t3 = trunc i32 %arg to i16
455 define i1 @oneuse_with_signbit(i32 %arg) {
457 ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
459 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 128
463 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
466 %t1 = icmp sgt i32 %arg, -1
468 %t2 = add i32 %arg, 128
476 define i1 @oneuse_with_signbit_logical(i32 %arg) {
478 ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
480 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 128
484 ; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
487 %t1 = icmp sgt i32 %arg, -1
489 %t2 = add i32 %arg, 128
497 define i1 @oneuse_with_mask(i32 %arg) {
499 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 603979776
503 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
507 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
510 %t1 = and i32 %arg, 603979776 ; some bit within the target 4294967168 mask.
514 %t3 = add i32 %arg, 128
522 define i1 @oneuse_with_mask_logical(i32 %arg) {
524 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 603979776
528 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
532 ; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
535 %t1 = and i32 %arg, 603979776 ; some bit within the target 4294967168 mask.
539 %t3 = add i32 %arg, 128
547 define i1 @oneuse_shl_ashr(i32 %arg) {
549 ; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i8
553 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[ARG]], 24
557 ; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], [[ARG]]
562 %t1 = trunc i32 %arg to i8
566 %t3 = shl i32 %arg, 24
570 %t5 = icmp eq i32 %t4, %arg
576 define i1 @oneuse_shl_ashr_logical(i32 %arg) {
578 ; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i8
582 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[ARG]], 24
586 ; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], [[ARG]]
591 %t1 = trunc i32 %arg to i8
595 %t3 = shl i32 %arg, 24
599 %t5 = icmp eq i32 %t4, %arg
605 define zeroext i1 @oneuse_trunc_sext(i32 %arg) {
607 ; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i8
611 ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[ARG]] to i8
615 ; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[ARG]], [[T4]]
620 %t1 = trunc i32 %arg to i8
624 %t3 = trunc i32 %arg to i8
628 %t5 = icmp eq i32 %t4, %arg
634 define zeroext i1 @oneuse_trunc_sext_logical(i32 %arg) {
636 ; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i8
640 ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[ARG]] to i8
644 ; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[ARG]], [[T4]]
649 %t1 = trunc i32 %arg to i8
653 %t3 = trunc i32 %arg to i8
657 %t5 = icmp eq i32 %t4, %arg
667 define i1 @negative_not_arg(i32 %arg, i32 %arg2) {
669 ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
675 %t1 = icmp sgt i32 %arg, -1
676 %t2 = add i32 %arg2, 128 ; not %arg
682 define i1 @negative_not_arg_logical(i32 %arg, i32 %arg2) {
684 ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
690 %t1 = icmp sgt i32 %arg, -1
691 %t2 = add i32 %arg2, 128 ; not %arg
697 define i1 @negative_trunc_not_arg(i32 %arg, i32 %arg2) {
699 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 128
706 %t1 = trunc i32 %arg to i8
708 %t3 = add i32 %arg2, 128 ; not %arg
714 define i1 @negative_trunc_not_arg_logical(i32 %arg, i32 %arg2) {
716 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 128
723 %t1 = trunc i32 %arg to i8
725 %t3 = add i32 %arg2, 128 ; not %arg
731 define i1 @positive_with_mask_not_arg(i32 %arg, i32 %arg2) {
733 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 1140850688
740 %t1 = and i32 %arg, 1140850688
742 %t3 = add i32 %arg2, 128 ; not %arg
748 define i1 @positive_with_mask_not_arg_logical(i32 %arg, i32 %arg2) {
750 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 1140850688
757 %t1 = and i32 %arg, 1140850688
759 %t3 = add i32 %arg2, 128 ; not %arg
765 define i1 @negative_with_nonuniform_bad_mask(i32 %arg) {
767 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 1711276033
769 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
774 %t1 = and i32 %arg, 1711276033 ; lowest bit is set
776 %t3 = add i32 %arg, 128
782 define i1 @negative_with_nonuniform_bad_mask_logical(i32 %arg) {
784 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 1711276033
786 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
791 %t1 = and i32 %arg, 1711276033 ; lowest bit is set
793 %t3 = add i32 %arg, 128
799 define i1 @negative_with_uniform_bad_mask(i32 %arg) {
801 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], -16777152
803 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
808 %t1 = and i32 %arg, 4278190144 ; 7'th bit is set
810 %t3 = add i32 %arg, 128
816 define i1 @negative_with_uniform_bad_mask_logical(i32 %arg) {
818 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], -16777152
820 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
825 %t1 = and i32 %arg, 4278190144 ; 7'th bit is set
827 %t3 = add i32 %arg, 128
833 define i1 @negative_with_wrong_mask(i32 %arg) {
835 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 1
837 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
842 %t1 = and i32 %arg, 1 ; not even checking the right mask
844 %t3 = add i32 %arg, 128
850 define i1 @negative_with_wrong_mask_logical(i32 %arg) {
852 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 1
854 ; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
859 %t1 = and i32 %arg, 1 ; not even checking the right mask
861 %t3 = add i32 %arg, 128
867 define i1 @negative_not_less_than(i32 %arg) {
871 %t1 = icmp sgt i32 %arg, -1
872 %t2 = add i32 %arg, 256 ; should be less than 256
878 define i1 @negative_not_less_than_logical(i32 %arg) {
882 %t1 = icmp sgt i32 %arg, -1
883 %t2 = add i32 %arg, 256 ; should be less than 256
889 define i1 @negative_not_power_of_two(i32 %arg) {
891 ; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[ARG:%.*]], 0
894 %t1 = icmp sgt i32 %arg, -1
895 %t2 = add i32 %arg, 255 ; should be power of two
901 define i1 @negative_not_power_of_two_logical(i32 %arg) {
903 ; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[ARG:%.*]], 0
906 %t1 = icmp sgt i32 %arg, -1
907 %t2 = add i32 %arg, 255 ; should be power of two
913 define i1 @negative_not_next_power_of_two(i32 %arg) {
915 ; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[ARG:%.*]], 192
918 %t1 = icmp sgt i32 %arg, -1
919 %t2 = add i32 %arg, 64 ; should be 256 >> 1
925 define i1 @negative_not_next_power_of_two_logical(i32 %arg) {
927 ; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[ARG:%.*]], 192
930 %t1 = icmp sgt i32 %arg, -1
931 %t2 = add i32 %arg, 64 ; should be 256 >> 1
937 define i1 @two_signed_truncation_checks(i32 %arg) {
939 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[ARG:%.*]], 128
943 %t1 = add i32 %arg, 512
945 %t3 = add i32 %arg, 128
951 define i1 @two_signed_truncation_checks_logical(i32 %arg) {
953 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[ARG:%.*]], 128
957 %t1 = add i32 %arg, 512
959 %t3 = add i32 %arg, 128
965 define i1 @bad_trunc_stc(i32 %arg) {
967 ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
968 ; CHECK-NEXT: [[T2:%.*]] = trunc i32 [[ARG]] to i16
974 %t1 = icmp sgt i32 %arg, -1 ; checks a bit outside of the i16
975 %t2 = trunc i32 %arg to i16
982 define i1 @bad_trunc_stc_logical(i32 %arg) {
984 ; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
985 ; CHECK-NEXT: [[T2:%.*]] = trunc i32 [[ARG]] to i16
991 %t1 = icmp sgt i32 %arg, -1 ; checks a bit outside of the i16
992 %t2 = trunc i32 %arg to i16