Lines Matching full:mul

12   %mul = mul i8 %x, 44
13   %and = and i8 %mul, 4
18 ; TODO: Demanded bits does not convert the mul to shift,
23 ; CHECK-NEXT:    [[MUL:%.*]] = mul i8 [[X:%.*]], 40
24 ; CHECK-NEXT:    call void @use(i8 [[MUL]])
25 ; CHECK-NEXT:    [[AND:%.*]] = and i8 [[MUL]], 8
29   %mul = mul i8 %x, 40
30   call void @use(i8 %mul)
31   %and = and i8 %mul, 8
40 ; CHECK-NEXT:    [[MUL:%.*]] = shl i8 [[X:%.*]], 3
41 ; CHECK-NEXT:    [[AND:%.*]] = and i8 [[MUL]], 8
46   %mul = mul i8 %x, 40
47   %and = and i8 %mul, 8
61   %mul = mul i8 %x, 44
62   %and = and i8 %mul, 4
75   %mul = mul i8 %x, 44
76   %and = and i8 %mul, 5
89   %mul = mul i8 %x, 44
90   %and = and i8 %mul, 4
99 ; CHECK-NEXT:    [[MUL:%.*]] = mul i8 [[X:%.*]], 12
100 ; CHECK-NEXT:    [[AND:%.*]] = and i8 [[MUL]], 12
104   %mul = mul i8 %x, 60
105   %and = and i8 %mul, 12
116   %mul = mul i32 %area, 12
117   %rem = and i32 %mul, 4
124 ; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[AREA:%.*]], 3
125 ; CHECK-NEXT:    [[REM:%.*]] = and i32 [[MUL]], 4
129   %mul = mul i32 %area, 11
130   %rem = and i32 %mul, 4
137 ; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[AREA:%.*]], 12
138 ; CHECK-NEXT:    [[REM:%.*]] = and i32 [[MUL]], 12
142   %mul = mul i32 %area, 12
143   %rem = and i32 %mul, 15
150 ; CHECK-NEXT:    [[MUL:%.*]] = shl i32 [[AREA:%.*]], 2
151 ; CHECK-NEXT:    [[REM:%.*]] = and i32 [[MUL]], 4
154   %mul = mul i32 %area, 12
155   %rem = and i32 %mul, 4
165   %mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 12>
166   %rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 4>
173 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 12, i32 undef>
174 ; CHECK-NEXT:    [[REM:%.*]] = and <4 x i32> [[MUL]], splat (i32 4)
178   %mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 undef>
179   %rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 4>
186 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], splat (i32 12)
187 ; CHECK-NEXT:    [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 4, i32 4, i32 4, i32 undef>
191   %mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 12>
192   %rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 undef>
199 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 12, i32 undef>
200 ; CHECK-NEXT:    [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 4, i32 4, i32 4, i32 undef>
204   %mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 undef>
205   %rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 undef>
212 ; CHECK-NEXT:    [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 20, i32 20>
213 ; CHECK-NEXT:    [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 2, i32 4, i32 2, i32 4>
217   %mul = mul <4 x i32> %area, <i32 12, i32 12, i32 20, i32 20>
218   %rem = and <4 x i32> %mul, <i32 2, i32 4, i32 2, i32 4>
231   %mul = mul nsw i32 %t1, %x
232   %and = and i32 %mul, 3
245   %mul = mul nsw i32 %t1, %x
246   %and = and i32 %mul, 1
255 ; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[T1]], [[X:%.*]]
256 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[MUL]], 7
262   %mul = mul nsw i32 %t1, %x
263   %and = and i32 %mul, 7
278   %mul = mul nsw i32 %t0, %x
279   %and = and i32 %mul, 7
291   %mul = mul nsw i32 %t1, %x
292   %and = and i32 %mul, 7