Lines Matching full:pr

5 …2-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"| FileCheck %s -check-prefixes=CHECK,PR-79158
29 ; PR-79158-LABEL: @simple1(
30 ; PR-79158-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16
31 ; PR-79158-NEXT:    [[T21:%.*]] = add i16 [[TMP1]], 1
32 ; PR-79158-NEXT:    ret i16 [[T21]]
59 ; PR-79158-LABEL: @simple2(
60 ; PR-79158-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16
61 ; PR-79158-NEXT:    [[T21:%.*]] = sub i16 [[TMP1]], 1
62 ; PR-79158-NEXT:    [[TMP2:%.*]] = trunc i16 [[T21]] to i8
63 ; PR-79158-NEXT:    ret i8 [[TMP2]]
89 ; PR-79158-LABEL: @simple3(
90 ; PR-79158-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16
91 ; PR-79158-NEXT:    [[T21:%.*]] = sub i16 [[TMP1]], 1
92 ; PR-79158-NEXT:    [[TMP2:%.*]] = zext i16 [[T21]] to i32
93 ; PR-79158-NEXT:    ret i32 [[TMP2]]
120 ; PR-79158-LABEL: @cmp(
121 ; PR-79158-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16
122 ; PR-79158-NEXT:    [[TMP2:%.*]] = zext i8 [[B:%.*]] to i16
123 ; PR-79158-NEXT:    [[T31:%.*]] = icmp slt i16 [[TMP1]], [[TMP2]]
124 ; PR-79158-NEXT:    ret i1 [[T31]]
168 ; PR-79158-LABEL: @simple5(
169 ; PR-79158-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32
170 ; PR-79158-NEXT:    [[TMP2:%.*]] = zext i8 [[B:%.*]] to i32
171 ; PR-79158-NEXT:    [[T31:%.*]] = add i32 [[TMP1]], 1
172 ; PR-79158-NEXT:    [[T42:%.*]] = mul i32 [[T31]], [[TMP2]]
173 ; PR-79158-NEXT:    ret i32 [[T42]]
206 ; PR-79158-LABEL: @simple6(
207 ; PR-79158-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i32
208 ; PR-79158-NEXT:    [[TMP2:%.*]] = zext i8 [[B:%.*]] to i32
209 ; PR-79158-NEXT:    [[T31:%.*]] = sub i32 0, [[TMP1]]
210 ; PR-79158-NEXT:    [[T42:%.*]] = mul i32 [[T31]], [[TMP2]]
211 ; PR-79158-NEXT:    ret i32 [[T42]]
257 ; PR-79158-LABEL: @multi1(
258 ; PR-79158-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16
259 ; PR-79158-NEXT:    [[TMP2:%.*]] = zext i8 [[B:%.*]] to i16
260 ; PR-79158-NEXT:    [[FC:%.*]] = uitofp i8 [[C:%.*]] to float
261 ; PR-79158-NEXT:    [[X1:%.*]] = add i16 [[TMP1]], [[TMP2]]
262 ; PR-79158-NEXT:    [[TMP3:%.*]] = zext i16 [[X1]] to i32
263 ; PR-79158-NEXT:    [[Z:%.*]] = fadd float [[FC]], [[D:%.*]]
264 ; PR-79158-NEXT:    [[W:%.*]] = fptoui float [[Z]] to i32
265 ; PR-79158-NEXT:    [[R:%.*]] = add i32 [[TMP3]], [[W]]
266 ; PR-79158-NEXT:    ret i32 [[R]]
297 ; PR-79158-LABEL: @simple_negzero(
298 ; PR-79158-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16
299 ; PR-79158-NEXT:    [[T21:%.*]] = add i16 [[TMP1]], 0
300 ; PR-79158-NEXT:    ret i16 [[T21]]
330 ; PR-79158-LABEL: @simple_negative(
331 ; PR-79158-NEXT:    [[TMP1:%.*]] = sext i8 [[CALL:%.*]] to i16
332 ; PR-79158-NEXT:    [[MUL1:%.*]] = mul i16 [[TMP1]], -3
333 ; PR-79158-NEXT:    [[TMP2:%.*]] = trunc i16 [[MUL1]] to i8
334 ; PR-79158-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
335 ; PR-79158-NEXT:    ret i32 [[CONV3]]
362 ; PR-79158-LABEL: @simple_fneg(
363 ; PR-79158-NEXT:    [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16
364 ; PR-79158-NEXT:    [[T21:%.*]] = sub i16 0, [[TMP1]]
365 ; PR-79158-NEXT:    ret i16 [[T21]]