Lines Matching +full:release +full:- +full:version

1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
2 ; RUN: opt -S -passes=early-cse -earlycse-debug-hash < %s | FileCheck %s
7 ; version of the memory model.  If we want to extend EarlyCSE to be more
13 ; CHECK-LABEL: define i32 @test
14 ; CHECK-SAME: (ptr [[ADDR_I:%.*]]) {
15 ; CHECK-NEXT:    store i32 5, ptr [[ADDR_I]], align 4
16 ; CHECK-NEXT:    fence release
17 ; CHECK-NEXT:    ret i32 5
20   fence release
27 ; CHECK-LABEL: define i32 @test2
28 ; CHECK-SAME: (ptr noalias [[ADDR_I:%.*]], ptr noalias [[OTHERADDR:%.*]]) {
29 ; CHECK-NEXT:    [[A:%.*]] = load i32, ptr [[ADDR_I]], align 4
30 ; CHECK-NEXT:    fence release
31 ; CHECK-NEXT:    ret i32 [[A]]
34   fence release
42 ; followed by a release fence.  If this thread observed the release
48 ; CHECK-LABEL: define i32 @test3
49 ; CHECK-SAME: (ptr noalias [[ADDR_I:%.*]], ptr noalias [[OTHERADDR:%.*]]) {
50 ; CHECK-NEXT:    [[A:%.*]] = load i32, ptr [[ADDR_I]], align 4
51 ; CHECK-NEXT:    fence acquire
52 ; CHECK-NEXT:    [[A2:%.*]] = load i32, ptr [[ADDR_I]], align 4
53 ; CHECK-NEXT:    [[RES:%.*]] = sub i32 [[A]], [[A2]]
54 ; CHECK-NEXT:    ret i32 [[RES]]
65 ; store, but this is beyond the simple last-store DSE which EarlyCSE
68 ; CHECK-LABEL: define void @test4
69 ; CHECK-SAME: (ptr [[ADDR_I:%.*]]) {
70 ; CHECK-NEXT:    store i32 5, ptr [[ADDR_I]], align 4
71 ; CHECK-NEXT:    fence release
72 ; CHECK-NEXT:    store i32 5, ptr [[ADDR_I]], align 4
73 ; CHECK-NEXT:    ret void
76   fence release
84 ; CHECK-LABEL: define void @test5
85 ; CHECK-SAME: (ptr [[ADDR_I:%.*]]) {
86 ; CHECK-NEXT:    store i32 5, ptr [[ADDR_I]], align 4
87 ; CHECK-NEXT:    fence acquire
88 ; CHECK-NEXT:    store i32 5, ptr [[ADDR_I]], align 4
89 ; CHECK-NEXT:    ret void