Lines Matching +full:0 +full:xee
8 # CHECK: vabav.s8 r0, q1, q3 @ encoding: [0x82,0xee,0x07,0x0f]
11 # CHECK: vabav.s16 r0, q1, q3 @ encoding: [0x92,0xee,0x07,0x0f]
14 # CHECK: vabav.s32 r0, q1, q3 @ encoding: [0xa2,0xee,0x07,0x0f]
17 # CHECK: vabav.u8 r0, q1, q3 @ encoding: [0x82,0xfe,0x07,0x0f]
20 # CHECK: vabav.u16 r0, q1, q3 @ encoding: [0x92,0xfe,0x07,0x0f]
23 # CHECK: vabav.u32 r0, q1, q3 @ encoding: [0xa2,0xfe,0x07,0x0f]
26 # CHECK: vaddv.s16 lr, q0 @ encoding: [0xf5,0xee,0x00,0xef]
33 # CHECK: vaddvt.s16 r0, q6 @ encoding: [0xf5,0xee,0x0c,0x0f]
34 # CHECK: vaddve.s16 r0, q6 @ encoding: [0xf5,0xee,0x0c,0x0f]
39 # CHECK: vaddva.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
43 # CHECK: vaddvat.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
44 # CHECK: vaddvae.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
49 # CHECK: vaddlv.s32 r0, r9, q2 @ encoding: [0xc9,0xee,0x04,0x0f]
52 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range …
55 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register
58 # CHECK: vaddlv.u32 r0, r1, q1 @ encoding: [0x89,0xfe,0x02,0x0f]
61 # CHECK: vminv.s8 lr, q0 @ encoding: [0xe2,0xee,0x80,0xef]
64 # CHECK: vminv.s16 lr, q0 @ encoding: [0xe6,0xee,0x80,0xef]
67 # CHECK: vminv.s32 lr, q2 @ encoding: [0xea,0xee,0x84,0xef]
70 # CHECK: vminv.u8 r0, q0 @ encoding: [0xe2,0xfe,0x80,0x0f]
73 # CHECK: vminv.u32 r10, q3 @ encoding: [0xea,0xfe,0x86,0xaf]
76 # CHECK: vminav.s16 r0, q0 @ encoding: [0xe4,0xee,0x80,0x0f]
79 # CHECK: vminav.s8 r0, q1 @ encoding: [0xe0,0xee,0x82,0x0f]
82 # CHECK: vminav.s32 lr, q1 @ encoding: [0xe8,0xee,0x82,0xef]
85 # CHECK: vmaxv.s8 lr, q4 @ encoding: [0xe2,0xee,0x08,0xef]
88 # CHECK: vmaxv.s16 lr, q0 @ encoding: [0xe6,0xee,0x00,0xef]
91 # CHECK: vmaxv.s32 r1, q1 @ encoding: [0xea,0xee,0x02,0x1f]
94 # CHECK: vmaxv.u8 r0, q4 @ encoding: [0xe2,0xfe,0x08,0x0f]
97 # CHECK: vmaxv.u16 r0, q1 @ encoding: [0xe6,0xfe,0x02,0x0f]
100 # CHECK: vmaxv.u32 r1, q0 @ encoding: [0xea,0xfe,0x00,0x1f]
103 # CHECK: vmaxav.s8 lr, q6 @ encoding: [0xe0,0xee,0x0c,0xef]
106 # CHECK: vmaxav.s16 r0, q6 @ encoding: [0xe4,0xee,0x0c,0x0f]
109 # CHECK: vmaxav.s32 r10, q7 @ encoding: [0xe8,0xee,0x0e,0xaf]
112 # CHECK: vmlav.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x0e,0xee]
115 # CHECK: vmlav.s32 lr, q0, q4 @ encoding: [0xf1,0xee,0x08,0xee]
118 # CHECK: vmlav.u16 lr, q0, q7 @ encoding: [0xf0,0xfe,0x0e,0xee]
121 # CHECK: vmlav.u32 lr, q0, q0 @ encoding: [0xf1,0xfe,0x00,0xee]
124 # CHECK: vmlava.s16 lr, q0, q4 @ encoding: [0xf0,0xee,0x28,0xee]
127 # CHECK: vmladavx.s16 r0, q0, q7 @ encoding: [0xf0,0xee,0x0e,0x1e]
130 # CHECK: vmladavax.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x2e,0xfe]
133 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
136 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
139 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
142 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
145 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
148 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
151 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
154 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
157 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
160 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
163 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
166 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
169 # CHECK: vmlav.s8 lr, q3, q0 @ encoding: [0xf6,0xee,0x00,0xef]
172 # CHECK: vmlav.u8 lr, q1, q7 @ encoding: [0xf2,0xfe,0x0e,0xef]
175 # CHECK: vrmlalvh.s32 lr, r1, q6, q2 @ encoding: [0x8c,0xee,0x04,0xef]
178 # CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
181 # CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
184 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register
187 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range …
190 # CHECK: vrmlaldavhax.s32 lr, r1, q3, q0 @ encoding: [0x86,0xee,0x20,0xff]
193 # CHECK: vrmlsldavh.s32 lr, r11, q6, q5 @ encoding: [0xdc,0xfe,0x0b,0xee]
196 # CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]
199 # CHECK: vrmlalvh.s32 lr, r1, q6, q2 @ encoding: [0x8c,0xee,0x04,0xef]
202 # CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
205 # CHECK: vrmlalvha.s32 lr, r1, q3, q6 @ encoding: [0x86,0xee,0x2c,0xef]
208 # CHECK: vrmlalvha.u32 lr, r1, q7, q1 @ encoding: [0x8e,0xfe,0x22,0xef]
211 # CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]
214 # CHECK: vmlsdav.s32 lr, q2, q6 @ encoding: [0xf5,0xee,0x0d,0xee]
218 # CHECK: vmlsdavaxt.s16 lr, q1, q4 @ encoding: [0xf2,0xee,0x29,0xfe]
219 # CHECK: vmlsdavaxe.s16 lr, q1, q4 @ encoding: [0xf2,0xee,0x29,0xfe]
224 # CHECK: vmlav.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x0e,0xee]
227 # CHECK: vmlalv.s16 lr, r1, q4, q1 @ encoding: [0x88,0xee,0x02,0xee]
230 # CHECK: vmlalv.s32 lr, r11, q4, q1 @ encoding: [0xd9,0xee,0x02,0xee]
233 # CHECK: vmlalv.s32 r0, r1, q7, q6 @ encoding: [0x8f,0xee,0x0c,0x0e]
236 # CHECK: vmlalv.u16 lr, r11, q5, q4 @ encoding: [0xda,0xfe,0x08,0xee]