Lines Matching refs:pvsrl
160 ; CHECK-NEXT: pvsrl %v0, %v0, %v1
162 …%3 = tail call fast <256 x double> @llvm.ve.vl.pvsrl.vvvl(<256 x double> %0, <256 x double> %1, i3…
167 declare <256 x double> @llvm.ve.vl.pvsrl.vvvl(<256 x double>, <256 x double>, i32)
175 ; CHECK-NEXT: pvsrl %v2, %v0, %v1
180 …%4 = tail call fast <256 x double> @llvm.ve.vl.pvsrl.vvvvl(<256 x double> %0, <256 x double> %1, <…
185 declare <256 x double> @llvm.ve.vl.pvsrl.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
193 ; CHECK-NEXT: pvsrl %v0, %v0, %s0
195 %3 = tail call fast <256 x double> @llvm.ve.vl.pvsrl.vvsl(<256 x double> %0, i64 %1, i32 256)
200 declare <256 x double> @llvm.ve.vl.pvsrl.vvsl(<256 x double>, i64, i32)
208 ; CHECK-NEXT: pvsrl %v1, %v0, %s0
213 …%4 = tail call fast <256 x double> @llvm.ve.vl.pvsrl.vvsvl(<256 x double> %0, i64 %1, <256 x doubl…
218 declare <256 x double> @llvm.ve.vl.pvsrl.vvsvl(<256 x double>, i64, <256 x double>, i32)
226 ; CHECK-NEXT: pvsrl %v2, %v0, %v1, %vm2
231 …%5 = tail call fast <256 x double> @llvm.ve.vl.pvsrl.vvvMvl(<256 x double> %0, <256 x double> %1, …
236 declare <256 x double> @llvm.ve.vl.pvsrl.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x …
244 ; CHECK-NEXT: pvsrl %v1, %v0, %s0, %vm2
249 …%5 = tail call fast <256 x double> @llvm.ve.vl.pvsrl.vvsMvl(<256 x double> %0, i64 %1, <512 x i1> …
254 declare <256 x double> @llvm.ve.vl.pvsrl.vvsMvl(<256 x double>, i64, <512 x i1>, <256 x double>, i3…