Lines Matching refs:pvsla
454 ; CHECK-NEXT: pvsla %v0, %v0, %v1
456 …%3 = tail call fast <256 x double> @llvm.ve.vl.pvsla.vvvl(<256 x double> %0, <256 x double> %1, i3…
461 declare <256 x double> @llvm.ve.vl.pvsla.vvvl(<256 x double>, <256 x double>, i32)
469 ; CHECK-NEXT: pvsla %v2, %v0, %v1
474 …%4 = tail call fast <256 x double> @llvm.ve.vl.pvsla.vvvvl(<256 x double> %0, <256 x double> %1, <…
479 declare <256 x double> @llvm.ve.vl.pvsla.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
487 ; CHECK-NEXT: pvsla %v0, %v0, %s0
489 %3 = tail call fast <256 x double> @llvm.ve.vl.pvsla.vvsl(<256 x double> %0, i64 %1, i32 256)
494 declare <256 x double> @llvm.ve.vl.pvsla.vvsl(<256 x double>, i64, i32)
502 ; CHECK-NEXT: pvsla %v1, %v0, %s0
507 …%4 = tail call fast <256 x double> @llvm.ve.vl.pvsla.vvsvl(<256 x double> %0, i64 %1, <256 x doubl…
512 declare <256 x double> @llvm.ve.vl.pvsla.vvsvl(<256 x double>, i64, <256 x double>, i32)
520 ; CHECK-NEXT: pvsla %v2, %v0, %v1, %vm2
525 …%5 = tail call fast <256 x double> @llvm.ve.vl.pvsla.vvvMvl(<256 x double> %0, <256 x double> %1, …
530 declare <256 x double> @llvm.ve.vl.pvsla.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x …
538 ; CHECK-NEXT: pvsla %v1, %v0, %s0, %vm2
543 …%5 = tail call fast <256 x double> @llvm.ve.vl.pvsla.vvsMvl(<256 x double> %0, i64 %1, <512 x i1> …
548 declare <256 x double> @llvm.ve.vl.pvsla.vvsMvl(<256 x double>, i64, <512 x i1>, <256 x double>, i3…