emergency-spill.mir - OpenGrok cross reference for /llvm-project/llvm/test/CodeGen/Mips/msa/emergency-spill.mir

Lines Matching full:stack
3 # Test that estimated size of the stack leads to the creation of an emergency
103 stack:
136     SD killed $a0_64, %stack.1.a, 0 :: (store (s64) into %ir.1, align 16)
137     SD killed $a1_64, %stack.1.a, 8 :: (store (s64) into %ir.2)
138     $w0 = LD_B %stack.1.a, 0 :: (dereferenceable load (s128) from %ir.a)
139     SD killed $a2_64, %stack.2.b, 0 :: (store (s64) into %ir.4, align 16)
140     SD killed $a3_64, %stack.2.b, 8 :: (store (s64) into %ir.5)
141     $w1 = LD_B %stack.2.b, 0 :: (dereferenceable load (s128) from %ir.b)
142     ST_B killed $w0, %stack.3.a.addr, 0 :: (store (s128) into %ir.a.addr)
143     ST_B killed $w1, %stack.4.b.addr, 0 :: (store (s128) into %ir.b.addr)
144     SW $t0, %stack.5.c.addr, 0, implicit killed $t0_64 :: (store (s32) into %ir.c.addr)
145     $at_64 = LEA_ADDiu64 %stack.8, 0
146     SD killed $at_64, %stack.6.g, 0 :: (store (s64) into %ir.g)
147     $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
149     $a0_64 = LEA_ADDiu64 %stack.4.b.addr, 0
152     $at_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
153     $v0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
154     $v1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
155     $a0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
156     $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
157     $a2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
158     $a3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
159     $t0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
160     $t1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
161     $t2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
162     $t3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
163     $t4_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
164     $t5_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
165     $t6_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
166     $t7_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
167     $s0_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
168     $s1_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
169     $s2_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
170     $s3_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
171     $s4_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
172     $s5_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
173     $s6_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
174     $s7_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
175     $t8_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
176     $t9_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
177     $ra_64 = LD %stack.6.g, 0 :: (dereferenceable load (s64) from %ir.g)
178     $w0 = LD_B %stack.3.a.addr, 0 :: (dereferenceable load (s128) from %ir.a.addr)
179     SD $at_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
180     SD $v0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
181     SD $v1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
182     SD $a0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
183     SD $a1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
184     SD $a2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
185     SD $a3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
186     SD $t0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
187     SD $t1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
188     SD $t2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
189     SD $t3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
190     SD $t4_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
191     SD $t5_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
192     SD $t6_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
193     SD $t7_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
194     SD $s0_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
195     SD $s1_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
196     SD $s2_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
197     SD $s3_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
198     SD $s4_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
199     SD $s5_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
200     SD $s6_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
201     SD $s7_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
202     SD $t8_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
203     SD $t9_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
204     SD $ra_64, %stack.7.d, 0 :: (store (s64) into %ir.d)
205     $at_64 = LD %stack.7.d, 0 :: (dereferenceable load (s64) from %ir.d)
212     $w1 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load (s128) from %ir.b.addr)
214     ST_B killed $w0, %stack.4.b.addr, 0 :: (store (s128) into %ir.b.addr)
215     $w0 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load (s128) from %ir.b.addr)
216     ST_B killed $w0, %stack.0.retval, 0 :: (store (s128) into %ir.retval)
217     $v0_64 = LD %stack.0.retval, 0 :: (dereferenceable load (s64) from %ir.20, basealign 16)
218     $v1_64 = LD %stack.0.retval, 8 :: (dereferenceable load (s64) from %ir.20 + 8, basealign 16)