Lines Matching +full:cycle +full:- +full:frequency

1 ; RUN: llc -mtriple=arm -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | grep -v "Verify generated machine code" | FileCheck %s
6 ; CHECK-NEXT:    Pre-ISel Intrinsic Lowering
7 ; CHECK-NEXT:    FunctionPass Manager
8 ; CHECK-NEXT:      Expand large div/rem
9 ; CHECK-NEXT:      Expand large fp convert
10 ; CHECK-NEXT:      Expand Atomic instructions
11 ; CHECK-NEXT:      Simplify the CFG
12 ; CHECK-NEXT:      Dominator Tree Construction
13 ; CHECK-NEXT:      Natural Loop Information
14 ; CHECK-NEXT:      MVE gather/scatter lowering
15 ; CHECK-NEXT:      MVE lane interleaving
16 ; CHECK-NEXT:      Module Verifier
17 ; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
18 ; CHECK-NEXT:      Canonicalize natural loops
19 ; CHECK-NEXT:      Scalar Evolution Analysis
20 ; CHECK-NEXT:      Loop Pass Manager
21 ; CHECK-NEXT:        Canonicalize Freeze Instructions in Loops
22 ; CHECK-NEXT:        Induction Variable Users
23 ; CHECK-NEXT:        Loop Strength Reduction
24 ; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
25 ; CHECK-NEXT:      Function Alias Analysis Results
26 ; CHECK-NEXT:      Merge contiguous icmps into a memcmp
27 ; CHECK-NEXT:      Natural Loop Information
28 ; CHECK-NEXT:      Lazy Branch Probability Analysis
29 ; CHECK-NEXT:      Lazy Block Frequency Analysis
30 ; CHECK-NEXT:      Expand memcmp() to load/stores
31 ; CHECK-NEXT:      Lower Garbage Collection Instructions
32 ; CHECK-NEXT:      Shadow Stack GC Lowering
33 ; CHECK-NEXT:      Remove unreachable blocks from the CFG
34 ; CHECK-NEXT:      Natural Loop Information
35 ; CHECK-NEXT:      Post-Dominator Tree Construction
36 ; CHECK-NEXT:      Branch Probability Analysis
37 ; CHECK-NEXT:      Block Frequency Analysis
38 ; CHECK-NEXT:      Constant Hoisting
39 ; CHECK-NEXT:      Replace intrinsics with calls to vector library
40 ; CHECK-NEXT:      Lazy Branch Probability Analysis
41 ; CHECK-NEXT:      Lazy Block Frequency Analysis
42 ; CHECK-NEXT:      Optimization Remark Emitter
43 ; CHECK-NEXT:      Partially inline calls to library functions
44 ; CHECK-NEXT:      Instrument function entry/exit with calls to e.g. mcount() (post inlining)
45 ; CHECK-NEXT:      Scalarize Masked Memory Intrinsics
46 ; CHECK-NEXT:      Expand reduction intrinsics
47 ; CHECK-NEXT:      Natural Loop Information
48 ; CHECK-NEXT:      Scalar Evolution Analysis
49 ; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
50 ; CHECK-NEXT:      Function Alias Analysis Results
51 ; CHECK-NEXT:      Transform functions to use DSP intrinsics
52 ; CHECK-NEXT:      Complex Deinterleaving Pass
53 ; CHECK-NEXT:      Interleaved Access Pass
54 ; CHECK-NEXT:      Type Promotion
55 ; CHECK-NEXT:      CodeGen Prepare
56 ; CHECK-NEXT:      Dominator Tree Construction
57 ; CHECK-NEXT:      Exception handling preparation
58 ; CHECK-NEXT:      Merge internal globals
59 ; CHECK-NEXT:      Natural Loop Information
60 ; CHECK-NEXT:      Scalar Evolution Analysis
61 ; CHECK-NEXT:      Lazy Branch Probability Analysis
62 ; CHECK-NEXT:      Lazy Block Frequency Analysis
63 ; CHECK-NEXT:      Optimization Remark Emitter
64 ; CHECK-NEXT:      Hardware Loop Insertion
65 ; CHECK-NEXT:      Loop Pass Manager
66 ; CHECK-NEXT:        Transform predicated vector loops to use MVE tail predication
67 ; CHECK-NEXT:      A No-Op Barrier Pass
68 ; CHECK-NEXT:      FunctionPass Manager
69 ; CHECK-NEXT:      Dominator Tree Construction
70 ; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
71 ; CHECK-NEXT:      Function Alias Analysis Results
72 ; CHECK-NEXT:      ObjC ARC contraction
73 ; CHECK-NEXT:      Prepare callbr
74 ; CHECK-NEXT:      Safe Stack instrumentation pass
75 ; CHECK-NEXT:      Insert stack protectors
76 ; CHECK-NEXT:      Module Verifier
77 ; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
78 ; CHECK-NEXT:      Function Alias Analysis Results
79 ; CHECK-NEXT:      Natural Loop Information
80 ; CHECK-NEXT:      Post-Dominator Tree Construction
81 ; CHECK-NEXT:      Branch Probability Analysis
82 ; CHECK-NEXT:      Assignment Tracking Analysis
83 ; CHECK-NEXT:      Lazy Branch Probability Analysis
84 ; CHECK-NEXT:      Lazy Block Frequency Analysis
85 ; CHECK-NEXT:      ARM Instruction Selection
86 ; CHECK-NEXT:      Finalize ISel and expand pseudo-instructions
87 ; CHECK-NEXT:      Lazy Machine Block Frequency Analysis
88 ; CHECK-NEXT:      Early Tail Duplication
89 ; CHECK-NEXT:      Optimize machine instruction PHIs
90 ; CHECK-NEXT:      Slot index numbering
91 ; CHECK-NEXT:      Merge disjoint stack slots
92 ; CHECK-NEXT:      Local Stack Slot Allocation
93 ; CHECK-NEXT:      Remove dead machine instructions
94 ; CHECK-NEXT:      MachineDominator Tree Construction
95 ; CHECK-NEXT:      Machine Natural Loop Construction
96 ; CHECK-NEXT:      Machine Block Frequency Analysis
97 ; CHECK-NEXT:      Early Machine Loop Invariant Code Motion
98 ; CHECK-NEXT:      MachineDominator Tree Construction
99 ; CHECK-NEXT:      Machine Block Frequency Analysis
100 ; CHECK-NEXT:      Machine Common Subexpression Elimination
101 ; CHECK-NEXT:      MachinePostDominator Tree Construction
102 ; CHECK-NEXT:      Machine Cycle Info Analysis
103 ; CHECK-NEXT:      Machine code sinking
104 ; CHECK-NEXT:      Peephole Optimizations
105 ; CHECK-NEXT:      Remove dead machine instructions
106 ; CHECK-NEXT:      MachineDominator Tree Construction
107 ; CHECK-NEXT:      Slot index numbering
108 ; CHECK-NEXT:      Live Interval Analysis
109 ; CHECK-NEXT:      Lazy Machine Block Frequency Analysis
110 ; CHECK-NEXT:      Machine Optimization Remark Emitter
111 ; CHECK-NEXT:      Modulo Software Pipelining
112 ; CHECK-NEXT:      MachineDominator Tree Construction
113 ; CHECK-NEXT:      Machine Natural Loop Construction
114 ; CHECK-NEXT:      MVE TailPred and VPT Optimisation Pass
115 ; CHECK-NEXT:      ARM MLA / MLS expansion pass
116 ; CHECK-NEXT:      MachineDominator Tree Construction
117 ; CHECK-NEXT:      ARM pre- register allocation load / store optimization pass
118 ; CHECK-NEXT:      ARM A15 S->D optimizer
119 ; CHECK-NEXT:      Detect Dead Lanes
120 ; CHECK-NEXT:      Init Undef Pass
121 ; CHECK-NEXT:      Process Implicit Definitions
122 ; CHECK-NEXT:      Remove unreachable machine basic blocks
123 ; CHECK-NEXT:      Live Variable Analysis
124 ; CHECK-NEXT:      MachineDominator Tree Construction
125 ; CHECK-NEXT:      Machine Natural Loop Construction
126 ; CHECK-NEXT:      Eliminate PHI nodes for register allocation
127 ; CHECK-NEXT:      Two-Address instruction pass
128 ; CHECK-NEXT:      Slot index numbering
129 ; CHECK-NEXT:      Live Interval Analysis
130 ; CHECK-NEXT:      Register Coalescer
131 ; CHECK-NEXT:      Rename Disconnected Subregister Components
132 ; CHECK-NEXT:      Machine Instruction Scheduler
133 ; CHECK-NEXT:      Machine Block Frequency Analysis
134 ; CHECK-NEXT:      Debug Variable Analysis
135 ; CHECK-NEXT:      Live Stack Slot Analysis
136 ; CHECK-NEXT:      Virtual Register Map
137 ; CHECK-NEXT:      Live Register Matrix
138 ; CHECK-NEXT:      Bundle Machine CFG Edges
139 ; CHECK-NEXT:      Spill Code Placement Analysis
140 ; CHECK-NEXT:      Lazy Machine Block Frequency Analysis
141 ; CHECK-NEXT:      Machine Optimization Remark Emitter
142 ; CHECK-NEXT:      Greedy Register Allocator
143 ; CHECK-NEXT:      Virtual Register Rewriter
144 ; CHECK-NEXT:      Register Allocation Pass Scoring
145 ; CHECK-NEXT:      Stack Slot Coloring
146 ; CHECK-NEXT:      Machine Copy Propagation Pass
147 ; CHECK-NEXT:      Machine Loop Invariant Code Motion
148 ; CHECK-NEXT:      Remove Redundant DEBUG_VALUE analysis
149 ; CHECK-NEXT:      Fixup Statepoint Caller Saved
150 ; CHECK-NEXT:      PostRA Machine Sink
151 ; CHECK-NEXT:      Machine Block Frequency Analysis
152 ; CHECK-NEXT:      MachineDominator Tree Construction
153 ; CHECK-NEXT:      MachinePostDominator Tree Construction
154 ; CHECK-NEXT:      Lazy Machine Block Frequency Analysis
155 ; CHECK-NEXT:      Machine Optimization Remark Emitter
156 ; CHECK-NEXT:      Shrink Wrapping analysis
157 ; CHECK-NEXT:      Prologue/Epilogue Insertion & Frame Finalization
158 ; CHECK-NEXT:      Machine Late Instructions Cleanup Pass
159 ; CHECK-NEXT:      Control Flow Optimizer
160 ; CHECK-NEXT:      Lazy Machine Block Frequency Analysis
161 ; CHECK-NEXT:      Tail Duplication
162 ; CHECK-NEXT:      Machine Copy Propagation Pass
163 ; CHECK-NEXT:      Post-RA pseudo instruction expansion pass
164 ; CHECK-NEXT:      ARM load / store optimization pass
165 ; CHECK-NEXT:      ReachingDefAnalysis
166 ; CHECK-NEXT:      ARM Execution Domain Fix
167 ; CHECK-NEXT:      BreakFalseDeps
168 ; CHECK-NEXT:      ARM pseudo instruction expansion pass
169 ; CHECK-NEXT:      Thumb2 instruction size reduce pass
170 ; CHECK-NEXT:      MachineDominator Tree Construction
171 ; CHECK-NEXT:      Machine Natural Loop Construction
172 ; CHECK-NEXT:      Machine Block Frequency Analysis
173 ; CHECK-NEXT:      If Converter
174 ; CHECK-NEXT:      Thumb IT blocks insertion pass
175 ; CHECK-NEXT:      MachineDominator Tree Construction
176 ; CHECK-NEXT:      Machine Natural Loop Construction
177 ; CHECK-NEXT:      PostRA Machine Instruction Scheduler
178 ; CHECK-NEXT:      Post RA top-down list latency scheduler
179 ; CHECK-NEXT:      MVE VPT block insertion pass
180 ; CHECK-NEXT:      ARM Indirect Thunks
181 ; CHECK-NEXT:      ARM sls hardening pass
182 ; CHECK-NEXT:      Analyze Machine Code For Garbage Collection
183 ; CHECK-NEXT:      MachineDominator Tree Construction
184 ; CHECK-NEXT:      Machine Natural Loop Construction
185 ; CHECK-NEXT:      Machine Block Frequency Analysis
186 ; CHECK-NEXT:      MachinePostDominator Tree Construction
187 ; CHECK-NEXT:      Branch Probability Basic Block Placement
188 ; CHECK-NEXT:      Insert fentry calls
189 ; CHECK-NEXT:      Insert XRay ops
190 ; CHECK-NEXT:      Implement the 'patchable-function' attribute
191 ; CHECK-NEXT:      Thumb2 instruction size reduce pass
192 ; CHECK-NEXT:      Unpack machine instruction bundles
193 ; CHECK-NEXT:      MachineDominator Tree Construction
194 ; CHECK-NEXT:      Machine Natural Loop Construction
195 ; CHECK-NEXT:      ARM block placement
196 ; CHECK-NEXT:      optimise barriers pass
197 ; CHECK-NEXT:      Contiguously Lay Out Funclets
198 ; CHECK-NEXT:      Remove Loads Into Fake Uses
199 ; CHECK-NEXT:      StackMap Liveness Analysis
200 ; CHECK-NEXT:      Live DEBUG_VALUE analysis
201 ; CHECK-NEXT:      Machine Sanitizer Binary Metadata
202 ; CHECK-NEXT:    Machine Outliner
203 ; CHECK-NEXT:    FunctionPass Manager
204 ; CHECK-NEXT:      Lazy Machine Block Frequency Analysis
205 ; CHECK-NEXT:      Machine Optimization Remark Emitter
206 ; CHECK-NEXT:      Stack Frame Layout Analysis
207 ; CHECK-NEXT:      ReachingDefAnalysis
208 ; CHECK-NEXT:      ARM fix for Cortex-A57 AES Erratum 1742098
209 ; CHECK-NEXT:      ARM Branch Targets
210 ; CHECK-NEXT:      MachineDominator Tree Construction
211 ; CHECK-NEXT:      ARM constant island placement and branch shortening pass
212 ; CHECK-NEXT:      MachineDominator Tree Construction
213 ; CHECK-NEXT:      Machine Natural Loop Construction
214 ; CHECK-NEXT:      ReachingDefAnalysis
215 ; CHECK-NEXT:      ARM Low Overhead Loops pass
216 ; CHECK-NEXT:      Lazy Machine Block Frequency Analysis
217 ; CHECK-NEXT:      Machine Optimization Remark Emitter
218 ; CHECK-NEXT:      ARM Assembly Printer
219 ; CHECK-NEXT:      Free MachineFunction