Lines Matching refs:uxtw
237 ; LD1B, LD1W, LD1H, LD1D: base + 64-bit uxtw'd unscaled offset
238 ; e.g. ld1h { z0.d }, p0/z, [x0, z0.d, uxtw]
244 ; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, z0.d, uxtw]
246 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
251 <vscale x 2 x i64> %uxtw)
259 ; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, z0.d, uxtw]
261 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
266 <vscale x 2 x i64> %uxtw)
274 ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, z0.d, uxtw]
276 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
281 <vscale x 2 x i64> %uxtw)
289 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw]
291 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
296 <vscale x 2 x i64> %uxtw)
303 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw]
305 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
310 <vscale x 2 x i64> %uxtw)
315 ; LD1SB, LD1SW, LD1SH: base + 64-bit uxtw'd unscaled offset
322 ; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, z0.d, uxtw]
324 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
329 <vscale x 2 x i64> %uxtw)
337 ; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw]
339 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
344 <vscale x 2 x i64> %uxtw)
352 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw]
354 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
359 <vscale x 2 x i64> %uxtw)
371 declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <v…