Lines Matching refs:uxtw
184 ; e.g. ld1h z0.d, p0/z, [x0, z0.d, uxtw #1]
190 ; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
192 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
197 … <vscale x 2 x i64> %uxtw)
205 ; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
207 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
212 … <vscale x 2 x i64> %uxtw)
220 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
222 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
227 … <vscale x 2 x i64> %uxtw)
234 ; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
236 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
241 … <vscale x 2 x i64> %uxtw)
246 ; LD1SH, LD1SW: base + 64-bit uxtw'd scaled offset
247 ; e.g. ld1sh z0.d, p0/z, [x0, z0.d, uxtw #1]
253 ; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
255 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
260 … <vscale x 2 x i64> %uxtw)
268 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
270 %uxtw = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef,
275 … <vscale x 2 x i64> %uxtw)
286 declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <v…