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4 declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
5 declare <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>)
6 declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>)
7 declare <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>)
9 define <8 x i16> @haddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
12 ; CHECK-NEXT: uhadd v0.8b, v0.8b, v1.8b
13 ; CHECK-NEXT: ushll v0.8h, v0.8b, #0
15 %x0 = zext <8 x i8> %a0 to <8 x i16>
16 %x1 = zext <8 x i8> %a1 to <8 x i16>
17 %hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
18 …%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>
19 ret <8 x i16> %res
22 define <8 x i16> @rhaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
25 ; CHECK-NEXT: urhadd v0.8b, v0.8b, v1.8b
26 ; CHECK-NEXT: ushll v0.8h, v0.8b, #0
28 %x0 = zext <8 x i8> %a0 to <8 x i16>
29 %x1 = zext <8 x i8> %a1 to <8 x i16>
30 %hadd = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
31 …%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 51…
32 ret <8 x i16> %res
35 define <8 x i16> @hadds_zext(<8 x i8> %a0, <8 x i8> %a1) {
38 ; CHECK-NEXT: ushll v0.8h, v0.8b, #0
39 ; CHECK-NEXT: ushll v1.8h, v1.8b, #0
40 ; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
42 %x0 = zext <8 x i8> %a0 to <8 x i16>
43 %x1 = zext <8 x i8> %a1 to <8 x i16>
44 %hadd = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
45 …%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 51…
46 ret <8 x i16> %res
49 define <8 x i16> @shaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
52 ; CHECK-NEXT: ushll v0.8h, v0.8b, #0
53 ; CHECK-NEXT: ushll v1.8h, v1.8b, #0
54 ; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
56 %x0 = zext <8 x i8> %a0 to <8 x i16>
57 %x1 = zext <8 x i8> %a1 to <8 x i16>
58 %hadd = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
59 …%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 51…
60 ret <8 x i16> %res
65 define <8 x i16> @haddu_sext(<8 x i8> %a0, <8 x i8> %a1) {
68 ; CHECK-NEXT: sshll v0.8h, v0.8b, #0
69 ; CHECK-NEXT: sshll v1.8h, v1.8b, #0
70 ; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
71 ; CHECK-NEXT: bic v0.8h, #254, lsl #8
73 %x0 = sext <8 x i8> %a0 to <8 x i16>
74 %x1 = sext <8 x i8> %a1 to <8 x i16>
75 %hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
76 …%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>
77 ret <8 x i16> %res
80 define <8 x i16> @urhadd_sext(<8 x i8> %a0, <8 x i8> %a1) {
83 ; CHECK-NEXT: sshll v0.8h, v0.8b, #0
84 ; CHECK-NEXT: sshll v1.8h, v1.8b, #0
85 ; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
86 ; CHECK-NEXT: bic v0.8h, #254, lsl #8
88 %x0 = sext <8 x i8> %a0 to <8 x i16>
89 %x1 = sext <8 x i8> %a1 to <8 x i16>
90 %hadd = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
91 …%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>
92 ret <8 x i16> %res
95 define <8 x i16> @hadds_sext(<8 x i8> %a0, <8 x i8> %a1) {
98 ; CHECK-NEXT: shadd v0.8b, v0.8b, v1.8b
99 ; CHECK-NEXT: sshll v0.8h, v0.8b, #0
100 ; CHECK-NEXT: bic v0.8h, #254, lsl #8
102 %x0 = sext <8 x i8> %a0 to <8 x i16>
103 %x1 = sext <8 x i8> %a1 to <8 x i16>
104 %hadd = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
105 …%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 51…
106 ret <8 x i16> %res
109 define <8 x i16> @shaddu_sext(<8 x i8> %a0, <8 x i8> %a1) {
112 ; CHECK-NEXT: srhadd v0.8b, v0.8b, v1.8b
113 ; CHECK-NEXT: sshll v0.8h, v0.8b, #0
114 ; CHECK-NEXT: bic v0.8h, #254, lsl #8
116 %x0 = sext <8 x i8> %a0 to <8 x i16>
117 %x1 = sext <8 x i8> %a1 to <8 x i16>
118 %hadd = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
119 …%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 51…
120 ret <8 x i16> %res