Lines Matching defs:CFG

33 #include "llvm/IR/CFG.h"
221     : TTI(TTI), VF(VF), CFG(DT), LI(LI), Builder(Builder), ILV(ILV), Plan(Plan),
273           CFG.VPBB2IRBB[Plan->getVectorPreheader()];
404 VPBasicBlock::createEmptyBasicBlock(VPTransformState::CFGState &CFG) {
407   BasicBlock *PrevBB = CFG.PrevBB;
409                                          PrevBB->getParent(), CFG.ExitBB);
415 void VPBasicBlock::connectToPredecessors(VPTransformState::CFGState &CFG) {
416   BasicBlock *NewBB = CFG.VPBB2IRBB[this];
421     BasicBlock *PredBB = CFG.VPBB2IRBB[PredVPBB];
447     CFG.DTU.applyUpdates({{DominatorTree::Insert, PredBB, NewBB}});
455   State->CFG.PrevBB = IRBB;
456   State->CFG.VPBB2IRBB[this] = IRBB;
470   connectToPredecessors(State->CFG);
482   BasicBlock *NewBB = State->CFG.PrevBB; // Reuse it if possible.
495     State->CFG.VPBB2IRBB[this] = NewBB;
497     NewBB = createEmptyBasicBlock(State->CFG);
500     // Temporarily terminate with unreachable until CFG is rewired.
508     State->CFG.PrevBB = NewBB;
509     State->CFG.VPBB2IRBB[this] = NewBB;
510     connectToPredecessors(State->CFG);
528   State->CFG.PrevVPBB = this;
647 // Clone the CFG for all nodes reachable from \p Entry, this includes cloning
719     BasicBlock *VectorPH = State->CFG.VPBB2IRBB[getPreheaderVPBB()];
929     IRBuilder<> Builder(State.CFG.PrevBB->getTerminator());
937   IRBuilder<> Builder(State.CFG.PrevBB->getTerminator());
957   // Initialize CFG state.
958   State->CFG.PrevVPBB = nullptr;
959   State->CFG.ExitBB = State->CFG.PrevBB->getSingleSuccessor();
961   // Disconnect VectorPreHeader from ExitBB in both the CFG and DT.
962   BasicBlock *VectorPreHeader = State->CFG.PrevBB;
964   State->CFG.DTU.applyUpdates(
965       {{DominatorTree::Delete, VectorPreHeader, State->CFG.ExitBB}});
973   // header) in both the CFG and DT. The branch will be recreated during VPlan
975   BasicBlock *MiddleBB = State->CFG.ExitBB;
980   State->CFG.DTU.applyUpdates({{DominatorTree::Delete, MiddleBB, ScalarPh}});
984   State->CFG.DTU.applyUpdates(
994   State->CFG.DTU.flush();
1001   BasicBlock *VectorLatchBB = State->CFG.VPBB2IRBB[LatchVPBB];