Lines Matching defs:OpNo
78 uint32_t getMemRegEncoding(const MCInst &MI, unsigned OpNo,
82 uint32_t getImm8OpValue(const MCInst &MI, unsigned OpNo,
86 uint32_t getImm8_sh8OpValue(const MCInst &MI, unsigned OpNo,
90 uint32_t getImm12OpValue(const MCInst &MI, unsigned OpNo,
94 uint32_t getUimm4OpValue(const MCInst &MI, unsigned OpNo,
98 uint32_t getUimm5OpValue(const MCInst &MI, unsigned OpNo,
102 uint32_t getImm1_16OpValue(const MCInst &MI, unsigned OpNo,
106 uint32_t getImm1n_15OpValue(const MCInst &MI, unsigned OpNo,
110 uint32_t getImm32n_95OpValue(const MCInst &MI, unsigned OpNo,
114 uint32_t getShimm1_31OpValue(const MCInst &MI, unsigned OpNo,
118 uint32_t getB4constOpValue(const MCInst &MI, unsigned OpNo,
122 uint32_t getB4constuOpValue(const MCInst &MI, unsigned OpNo,
253 XtensaMCCodeEmitter::getMemRegEncoding(const MCInst &MI, unsigned OpNo,
256 assert(MI.getOperand(OpNo + 1).isImm());
258 uint32_t Res = static_cast<uint32_t>(MI.getOperand(OpNo + 1).getImm());
291 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
296 uint32_t XtensaMCCodeEmitter::getImm8OpValue(const MCInst &MI, unsigned OpNo,
299 const MCOperand &MO = MI.getOperand(OpNo);
308 XtensaMCCodeEmitter::getImm8_sh8OpValue(const MCInst &MI, unsigned OpNo,
311 const MCOperand &MO = MI.getOperand(OpNo);
321 XtensaMCCodeEmitter::getImm12OpValue(const MCInst &MI, unsigned OpNo,
324 const MCOperand &MO = MI.getOperand(OpNo);
333 XtensaMCCodeEmitter::getUimm4OpValue(const MCInst &MI, unsigned OpNo,
336 const MCOperand &MO = MI.getOperand(OpNo);
345 XtensaMCCodeEmitter::getUimm5OpValue(const MCInst &MI, unsigned OpNo,
348 const MCOperand &MO = MI.getOperand(OpNo);
357 XtensaMCCodeEmitter::getShimm1_31OpValue(const MCInst &MI, unsigned OpNo,
360 const MCOperand &MO = MI.getOperand(OpNo);
369 XtensaMCCodeEmitter::getImm1_16OpValue(const MCInst &MI, unsigned OpNo,
372 const MCOperand &MO = MI.getOperand(OpNo);
381 XtensaMCCodeEmitter::getImm1n_15OpValue(const MCInst &MI, unsigned OpNo,
384 const MCOperand &MO = MI.getOperand(OpNo);
397 XtensaMCCodeEmitter::getImm32n_95OpValue(const MCInst &MI, unsigned OpNo,
400 const MCOperand &MO = MI.getOperand(OpNo);
409 XtensaMCCodeEmitter::getB4constOpValue(const MCInst &MI, unsigned OpNo,
412 const MCOperand &MO = MI.getOperand(OpNo);
457 XtensaMCCodeEmitter::getB4constuOpValue(const MCInst &MI, unsigned OpNo,
460 const MCOperand &MO = MI.getOperand(OpNo);