Lines Matching defs:dl

60                                const DebugLoc &dl, const TargetInstrInfo &TII,
64   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
70                              const DebugLoc &dl, const TargetInstrInfo &TII,
75   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
80                           MachineBasicBlock::iterator MBBI, const DebugLoc &dl,
86   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
97                           MachineBasicBlock::iterator MBBI, const DebugLoc &dl,
105     BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
108       EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4);
120                            MachineBasicBlock::iterator MBBI, const DebugLoc &dl,
127     BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
190                              const DebugLoc &dl, const TargetInstrInfo &TII,
197     IfNeededLDAWSP(MBB, MBBI, dl, TII, OffsetFromTop, RemainingAdj);
200     BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
231   DebugLoc dl;
239     BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0);
261     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
266       EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4);
268       EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0);
281     IfNeededExtSP(MBB, MBBI, dl, TII, OffsetFromTop, Adjusted, FrameSize,
286     BuildMI(MBB, MBBI, dl, TII.get(Opcode))
293       EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, SpillList[i].Offset);
298   IfNeededExtSP(MBB, MBBI, dl, TII, FrameSize, Adjusted, FrameSize,
304     BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
306       EmitDefCfaRegister(MBB, MBBI, dl, TII, MF,
318       EmitCfiOffset(MBB, Pos, dl, TII, DRegNum, Offset);
330       EmitCfiOffset(MBB, MBBI, dl, TII,
333       EmitCfiOffset(MBB, MBBI, dl, TII,
346   DebugLoc dl = MBBI->getDebugLoc();
364     RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
369     BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg);
370     BuildMI(MBB, MBBI, dl, TII.get(XCore::BAU_1r)).addReg(EhHandlerReg);
383     BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
388   RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
392     IfNeededLDAWSP(MBB, MBBI, dl, TII, 0, RemainingAdj);
398       MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
406       BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(RemainingAdj);