Lines Matching defs:MBBI

59                                MachineBasicBlock::iterator MBBI,
64   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
69                              MachineBasicBlock::iterator MBBI,
75   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
80                           MachineBasicBlock::iterator MBBI, const DebugLoc &dl,
86   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
97                           MachineBasicBlock::iterator MBBI, const DebugLoc &dl,
105     BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
108       EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4);
120                            MachineBasicBlock::iterator MBBI, const DebugLoc &dl,
127     BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
189                              MachineBasicBlock::iterator MBBI,
197     IfNeededLDAWSP(MBB, MBBI, dl, TII, OffsetFromTop, RemainingAdj);
200     BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
224   MachineBasicBlock::iterator MBBI = MBB.begin();
239     BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0);
261     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
266       EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4);
268       EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0);
281     IfNeededExtSP(MBB, MBBI, dl, TII, OffsetFromTop, Adjusted, FrameSize,
286     BuildMI(MBB, MBBI, dl, TII.get(Opcode))
293       EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, SpillList[i].Offset);
298   IfNeededExtSP(MBB, MBBI, dl, TII, FrameSize, Adjusted, FrameSize,
304     BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
306       EmitDefCfaRegister(MBB, MBBI, dl, TII, MF,
330       EmitCfiOffset(MBB, MBBI, dl, TII,
333       EmitCfiOffset(MBB, MBBI, dl, TII,
343   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
346   DebugLoc dl = MBBI->getDebugLoc();
347   unsigned RetOpcode = MBBI->getOpcode();
364     RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
367     Register EhStackReg = MBBI->getOperand(0).getReg();
368     Register EhHandlerReg = MBBI->getOperand(1).getReg();
369     BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg);
370     BuildMI(MBB, MBBI, dl, TII.get(XCore::BAU_1r)).addReg(EhHandlerReg);
371     MBB.erase(MBBI);  // Erase the previous return instruction.
383     BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
388   RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
392     IfNeededLDAWSP(MBB, MBBI, dl, TII, 0, RemainingAdj);
398       MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
400       for (unsigned i = 3, e = MBBI->getNumOperands(); i < e; ++i)
401         MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
402       MBB.erase(MBBI);  // Erase the previous return instruction.
406       BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(RemainingAdj);