Lines Matching defs:ISD
269 int ISD = TLI->InstructionOpcodeToISD(Opcode);
270 assert(ISD && "Invalid opcode");
272 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() &&
322 ISD = X86ISD::PMULUDQ;
327 if (ISD == ISD::MUL && Op2Info.isConstant() &&
341 if ((ISD == ISD::SDIV || ISD == ISD::SREM) &&
351 if (ISD == ISD::SREM) {
363 if ((ISD == ISD::UDIV || ISD == ISD::UREM) &&
365 if (ISD == ISD::UDIV)
374 { ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
375 { ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
376 { ISD::SRA, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
377 { ISD::SHL, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
378 { ISD::SRL, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
379 { ISD::SRA, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
380 { ISD::SHL, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
381 { ISD::SRL, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
382 { ISD::SRA, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
387 CostTableLookup(GFNIUniformConstCostTable, ISD, LT.second))
392 { ISD::SHL, MVT::v16i8, { 1, 7, 2, 3 } }, // psllw + pand.
393 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand.
394 { ISD::SRA, MVT::v16i8, { 1, 8, 4, 5 } }, // psrlw, pand, pxor, psubb.
395 { ISD::SHL, MVT::v32i8, { 1, 8, 2, 3 } }, // psllw + pand.
396 { ISD::SRL, MVT::v32i8, { 1, 8, 2, 3 } }, // psrlw + pand.
397 { ISD::SRA, MVT::v32i8, { 1, 9, 4, 5 } }, // psrlw, pand, pxor, psubb.
398 { ISD::SHL, MVT::v64i8, { 1, 8, 2, 3 } }, // psllw + pand.
399 { ISD::SRL, MVT::v64i8, { 1, 8, 2, 3 } }, // psrlw + pand.
400 { ISD::SRA, MVT::v64i8, { 1, 9, 4, 6 } }, // psrlw, pand, pxor, psubb.
402 { ISD::SHL, MVT::v16i16, { 1, 1, 1, 1 } }, // psllw
403 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw
404 { ISD::SRA, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw
405 { ISD::SHL, MVT::v32i16, { 1, 1, 1, 1 } }, // psllw
406 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw
407 { ISD::SRA, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw
412 CostTableLookup(AVX512BWUniformConstCostTable, ISD, LT.second))
417 { ISD::SHL, MVT::v64i8, { 2, 12, 5, 6 } }, // psllw + pand.
418 { ISD::SRL, MVT::v64i8, { 2, 12, 5, 6 } }, // psrlw + pand.
419 { ISD::SRA, MVT::v64i8, { 3, 10, 12, 12 } }, // psrlw, pand, pxor, psubb.
421 { ISD::SHL, MVT::v16i16, { 2, 7, 4, 4 } }, // psllw + split.
422 { ISD::SRL, MVT::v16i16, { 2, 7, 4, 4 } }, // psrlw + split.
423 { ISD::SRA, MVT::v16i16, { 2, 7, 4, 4 } }, // psraw + split.
425 { ISD::SHL, MVT::v8i32, { 1, 1, 1, 1 } }, // pslld
426 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } }, // psrld
427 { ISD::SRA, MVT::v8i32, { 1, 1, 1, 1 } }, // psrad
428 { ISD::SHL, MVT::v16i32, { 1, 1, 1, 1 } }, // pslld
429 { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } }, // psrld
430 { ISD::SRA, MVT::v16i32, { 1, 1, 1, 1 } }, // psrad
432 { ISD::SRA, MVT::v2i64, { 1, 1, 1, 1 } }, // psraq
433 { ISD::SHL, MVT::v4i64, { 1, 1, 1, 1 } }, // psllq
434 { ISD::SRL, MVT::v4i64, { 1, 1, 1, 1 } }, // psrlq
435 { ISD::SRA, MVT::v4i64, { 1, 1, 1, 1 } }, // psraq
436 { ISD::SHL, MVT::v8i64, { 1, 1, 1, 1 } }, // psllq
437 { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } }, // psrlq
438 { ISD::SRA, MVT::v8i64, { 1, 1, 1, 1 } }, // psraq
440 { ISD::SDIV, MVT::v16i32, { 6 } }, // pmuludq sequence
441 { ISD::SREM, MVT::v16i32, { 8 } }, // pmuludq+mul+sub sequence
442 { ISD::UDIV, MVT::v16i32, { 5 } }, // pmuludq sequence
443 { ISD::UREM, MVT::v16i32, { 7 } }, // pmuludq+mul+sub sequence
448 CostTableLookup(AVX512UniformConstCostTable, ISD, LT.second))
453 { ISD::SHL, MVT::v16i8, { 1, 8, 2, 3 } }, // psllw + pand.
454 { ISD::SRL, MVT::v16i8, { 1, 8, 2, 3 } }, // psrlw + pand.
455 { ISD::SRA, MVT::v16i8, { 2, 10, 5, 6 } }, // psrlw, pand, pxor, psubb.
456 { ISD::SHL, MVT::v32i8, { 2, 8, 2, 4 } }, // psllw + pand.
457 { ISD::SRL, MVT::v32i8, { 2, 8, 2, 4 } }, // psrlw + pand.
458 { ISD::SRA, MVT::v32i8, { 3, 10, 5, 9 } }, // psrlw, pand, pxor, psubb.
460 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // psllw
461 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw
462 { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // psraw
463 { ISD::SHL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psllw
464 { ISD::SRL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psrlw
465 { ISD::SRA, MVT::v16i16,{ 2, 2, 1, 2 } }, // psraw
467 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, // pslld
468 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld
469 { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } }, // psrad
470 { ISD::SHL, MVT::v8i32, { 2, 2, 1, 2 } }, // pslld
471 { ISD::SRL, MVT::v8i32, { 2, 2, 1, 2 } }, // psrld
472 { ISD::SRA, MVT::v8i32, { 2, 2, 1, 2 } }, // psrad
474 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } }, // psllq
475 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, // psrlq
476 { ISD::SRA, MVT::v2i64, { 2, 3, 3, 3 } }, // psrad + shuffle.
477 { ISD::SHL, MVT::v4i64, { 2, 2, 1, 2 } }, // psllq
478 { ISD::SRL, MVT::v4i64, { 2, 2, 1, 2 } }, // psrlq
479 { ISD::SRA, MVT::v4i64, { 4, 4, 3, 6 } }, // psrad + shuffle + split.
481 { ISD::SDIV, MVT::v8i32, { 6 } }, // pmuludq sequence
482 { ISD::SREM, MVT::v8i32, { 8 } }, // pmuludq+mul+sub sequence
483 { ISD::UDIV, MVT::v8i32, { 5 } }, // pmuludq sequence
484 { ISD::UREM, MVT::v8i32, { 7 } }, // pmuludq+mul+sub sequence
489 CostTableLookup(AVX2UniformConstCostTable, ISD, LT.second))
494 { ISD::SHL, MVT::v16i8, { 2, 7, 2, 3 } }, // psllw + pand.
495 { ISD::SRL, MVT::v16i8, { 2, 7, 2, 3 } }, // psrlw + pand.
496 { ISD::SRA, MVT::v16i8, { 3, 9, 5, 6 } }, // psrlw, pand, pxor, psubb.
497 { ISD::SHL, MVT::v32i8, { 4, 7, 7, 8 } }, // 2*(psllw + pand) + split.
498 { ISD::SRL, MVT::v32i8, { 4, 7, 7, 8 } }, // 2*(psrlw + pand) + split.
499 { ISD::SRA, MVT::v32i8, { 7, 7, 12, 13 } }, // 2*(psrlw, pand, pxor, psubb) + split.
501 { ISD::SHL, MVT::v8i16, { 1, 2, 1, 1 } }, // psllw.
502 { ISD::SRL, MVT::v8i16, { 1, 2, 1, 1 } }, // psrlw.
503 { ISD::SRA, MVT::v8i16, { 1, 2, 1, 1 } }, // psraw.
504 { ISD::SHL, MVT::v16i16,{ 3, 6, 4, 5 } }, // psllw + split.
505 { ISD::SRL, MVT::v16i16,{ 3, 6, 4, 5 } }, // psrlw + split.
506 { ISD::SRA, MVT::v16i16,{ 3, 6, 4, 5 } }, // psraw + split.
508 { ISD::SHL, MVT::v4i32, { 1, 2, 1, 1 } }, // pslld.
509 { ISD::SRL, MVT::v4i32, { 1, 2, 1, 1 } }, // psrld.
510 { ISD::SRA, MVT::v4i32, { 1, 2, 1, 1 } }, // psrad.
511 { ISD::SHL, MVT::v8i32, { 3, 6, 4, 5 } }, // pslld + split.
512 { ISD::SRL, MVT::v8i32, { 3, 6, 4, 5 } }, // psrld + split.
513 { ISD::SRA, MVT::v8i32, { 3, 6, 4, 5 } }, // psrad + split.
515 { ISD::SHL, MVT::v2i64, { 1, 2, 1, 1 } }, // psllq.
516 { ISD::SRL, MVT::v2i64, { 1, 2, 1, 1 } }, // psrlq.
517 { ISD::SRA, MVT::v2i64, { 2, 3, 3, 3 } }, // psrad + shuffle.
518 { ISD::SHL, MVT::v4i64, { 3, 6, 4, 5 } }, // 2 x psllq + split.
519 { ISD::SRL, MVT::v4i64, { 3, 6, 4, 5 } }, // 2 x psllq + split.
520 { ISD::SRA, MVT::v4i64, { 5, 7, 8, 9 } }, // 2 x psrad + shuffle + split.
522 { ISD::SDIV, MVT::v8i32, { 14 } }, // 2*pmuludq sequence + split.
523 { ISD::SREM, MVT::v8i32, { 18 } }, // 2*pmuludq+mul+sub sequence + split.
524 { ISD::UDIV, MVT::v8i32, { 12 } }, // 2*pmuludq sequence + split.
525 { ISD::UREM, MVT::v8i32, { 16 } }, // 2*pmuludq+mul+sub sequence + split.
532 CostTableLookup(AVXUniformConstCostTable, ISD, LT.second))
537 { ISD::SHL, MVT::v16i8, { 1, 7, 2, 3 } }, // psllw + pand.
538 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand.
539 { ISD::SRA, MVT::v16i8, { 3, 9, 5, 6 } }, // psrlw, pand, pxor, psubb.
541 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // psllw.
542 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw.
543 { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // psraw.
545 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, // pslld
546 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } }, // psrld.
547 { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } }, // psrad.
549 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } }, // psllq.
550 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } }, // psrlq.
551 { ISD::SRA, MVT::v2i64, { 3, 5, 6, 6 } }, // 2 x psrad + shuffle.
553 { ISD::SDIV, MVT::v4i32, { 6 } }, // pmuludq sequence
554 { ISD::SREM, MVT::v4i32, { 8 } }, // pmuludq+mul+sub sequence
555 { ISD::UDIV, MVT::v4i32, { 5 } }, // pmuludq sequence
556 { ISD::UREM, MVT::v4i32, { 7 } }, // pmuludq+mul+sub sequence
563 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second))
568 { ISD::SDIV, MVT::v64i8, { 14 } }, // 2*ext+2*pmulhw sequence
569 { ISD::SREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
570 { ISD::UDIV, MVT::v64i8, { 14 } }, // 2*ext+2*pmulhw sequence
571 { ISD::UREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
573 { ISD::SDIV, MVT::v32i16, { 6 } }, // vpmulhw sequence
574 { ISD::SREM, MVT::v32i16, { 8 } }, // vpmulhw+mul+sub sequence
575 { ISD::UDIV, MVT::v32i16, { 6 } }, // vpmulhuw sequence
576 { ISD::UREM, MVT::v32i16, { 8 } }, // vpmulhuw+mul+sub sequence
581 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second))
586 { ISD::SDIV, MVT::v64i8, { 28 } }, // 4*ext+4*pmulhw sequence
587 { ISD::SREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence
588 { ISD::UDIV, MVT::v64i8, { 28 } }, // 4*ext+4*pmulhw sequence
589 { ISD::UREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence
591 { ISD::SDIV, MVT::v32i16, { 12 } }, // 2*vpmulhw sequence
592 { ISD::SREM, MVT::v32i16, { 16 } }, // 2*vpmulhw+mul+sub sequence
593 { ISD::UDIV, MVT::v32i16, { 12 } }, // 2*vpmulhuw sequence
594 { ISD::UREM, MVT::v32i16, { 16 } }, // 2*vpmulhuw+mul+sub sequence
596 { ISD::SDIV, MVT::v16i32, { 15 } }, // vpmuldq sequence
597 { ISD::SREM, MVT::v16i32, { 17 } }, // vpmuldq+mul+sub sequence
598 { ISD::UDIV, MVT::v16i32, { 15 } }, // vpmuludq sequence
599 { ISD::UREM, MVT::v16i32, { 17 } }, // vpmuludq+mul+sub sequence
604 CostTableLookup(AVX512ConstCostTable, ISD, LT.second))
609 { ISD::SDIV, MVT::v32i8, { 14 } }, // 2*ext+2*pmulhw sequence
610 { ISD::SREM, MVT::v32i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
611 { ISD::UDIV, MVT::v32i8, { 14 } }, // 2*ext+2*pmulhw sequence
612 { ISD::UREM, MVT::v32i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
614 { ISD::SDIV, MVT::v16i16, { 6 } }, // vpmulhw sequence
615 { ISD::SREM, MVT::v16i16, { 8 } }, // vpmulhw+mul+sub sequence
616 { ISD::UDIV, MVT::v16i16, { 6 } }, // vpmulhuw sequence
617 { ISD::UREM, MVT::v16i16, { 8 } }, // vpmulhuw+mul+sub sequence
619 { ISD::SDIV, MVT::v8i32, { 15 } }, // vpmuldq sequence
620 { ISD::SREM, MVT::v8i32, { 19 } }, // vpmuldq+mul+sub sequence
621 { ISD::UDIV, MVT::v8i32, { 15 } }, // vpmuludq sequence
622 { ISD::UREM, MVT::v8i32, { 19 } }, // vpmuludq+mul+sub sequence
626 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second))
631 { ISD::SDIV, MVT::v32i8, { 30 } }, // 4*ext+4*pmulhw sequence + split.
632 { ISD::SREM, MVT::v32i8, { 34 } }, // 4*ext+4*pmulhw+mul+sub sequence + split.
633 { ISD::UDIV, MVT::v32i8, { 30 } }, // 4*ext+4*pmulhw sequence + split.
634 { ISD::UREM, MVT::v32i8, { 34 } }, // 4*ext+4*pmulhw+mul+sub sequence + split.
636 { ISD::SDIV, MVT::v16i16, { 14 } }, // 2*pmulhw sequence + split.
637 { ISD::SREM, MVT::v16i16, { 18 } }, // 2*pmulhw+mul+sub sequence + split.
638 { ISD::UDIV, MVT::v16i16, { 14 } }, // 2*pmulhuw sequence + split.
639 { ISD::UREM, MVT::v16i16, { 18 } }, // 2*pmulhuw+mul+sub sequence + split.
641 { ISD::SDIV, MVT::v8i32, { 32 } }, // vpmuludq sequence
642 { ISD::SREM, MVT::v8i32, { 38 } }, // vpmuludq+mul+sub sequence
643 { ISD::UDIV, MVT::v8i32, { 32 } }, // 2*pmuludq sequence + split.
644 { ISD::UREM, MVT::v8i32, { 42 } }, // 2*pmuludq+mul+sub sequence + split.
648 if (const auto *Entry = CostTableLookup(AVXConstCostTable, ISD, LT.second))
653 { ISD::SDIV, MVT::v4i32, { 15 } }, // vpmuludq sequence
654 { ISD::SREM, MVT::v4i32, { 20 } }, // vpmuludq+mul+sub sequence
659 CostTableLookup(SSE41ConstCostTable, ISD, LT.second))
664 { ISD::SDIV, MVT::v16i8, { 14 } }, // 2*ext+2*pmulhw sequence
665 { ISD::SREM, MVT::v16i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
666 { ISD::UDIV, MVT::v16i8, { 14 } }, // 2*ext+2*pmulhw sequence
667 { ISD::UREM, MVT::v16i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence
669 { ISD::SDIV, MVT::v8i16, { 6 } }, // pmulhw sequence
670 { ISD::SREM, MVT::v8i16, { 8 } }, // pmulhw+mul+sub sequence
671 { ISD::UDIV, MVT::v8i16, { 6 } }, // pmulhuw sequence
672 { ISD::UREM, MVT::v8i16, { 8 } }, // pmulhuw+mul+sub sequence
674 { ISD::SDIV, MVT::v4i32, { 19 } }, // pmuludq sequence
675 { ISD::SREM, MVT::v4i32, { 24 } }, // pmuludq+mul+sub sequence
676 { ISD::UDIV, MVT::v4i32, { 15 } }, // pmuludq sequence
677 { ISD::UREM, MVT::v4i32, { 20 } }, // pmuludq+mul+sub sequence
681 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second))
686 { ISD::SHL, MVT::v16i8, { 3, 5, 5, 7 } }, // psllw + pand.
687 { ISD::SRL, MVT::v16i8, { 3,10, 5, 8 } }, // psrlw + pand.
688 { ISD::SRA, MVT::v16i8, { 4,12, 8,12 } }, // psrlw, pand, pxor, psubb.
689 { ISD::SHL, MVT::v32i8, { 4, 7, 6, 8 } }, // psllw + pand.
690 { ISD::SRL, MVT::v32i8, { 4, 8, 7, 9 } }, // psrlw + pand.
691 { ISD::SRA, MVT::v32i8, { 5,10,10,13 } }, // psrlw, pand, pxor, psubb.
692 { ISD::SHL, MVT::v64i8, { 4, 7, 6, 8 } }, // psllw + pand.
693 { ISD::SRL, MVT::v64i8, { 4, 8, 7,10 } }, // psrlw + pand.
694 { ISD::SRA, MVT::v64i8, { 5,10,10,15 } }, // psrlw, pand, pxor, psubb.
696 { ISD::SHL, MVT::v32i16, { 2, 4, 2, 3 } }, // psllw
697 { ISD::SRL, MVT::v32i16, { 2, 4, 2, 3 } }, // psrlw
698 { ISD::SRA, MVT::v32i16, { 2, 4, 2, 3 } }, // psrqw
703 CostTableLookup(AVX512BWUniformCostTable, ISD, LT.second))
708 { ISD::SHL, MVT::v32i16, { 5,10, 5, 7 } }, // psllw + split.
709 { ISD::SRL, MVT::v32i16, { 5,10, 5, 7 } }, // psrlw + split.
710 { ISD::SRA, MVT::v32i16, { 5,10, 5, 7 } }, // psraw + split.
712 { ISD::SHL, MVT::v16i32, { 2, 4, 2, 3 } }, // pslld
713 { ISD::SRL, MVT::v16i32, { 2, 4, 2, 3 } }, // psrld
714 { ISD::SRA, MVT::v16i32, { 2, 4, 2, 3 } }, // psrad
716 { ISD::SRA, MVT::v2i64, { 1, 2, 1, 2 } }, // psraq
717 { ISD::SHL, MVT::v4i64, { 1, 4, 1, 2 } }, // psllq
718 { ISD::SRL, MVT::v4i64, { 1, 4, 1, 2 } }, // psrlq
719 { ISD::SRA, MVT::v4i64, { 1, 4, 1, 2 } }, // psraq
720 { ISD::SHL, MVT::v8i64, { 1, 4, 1, 2 } }, // psllq
721 { ISD::SRL, MVT::v8i64, { 1, 4, 1, 2 } }, // psrlq
722 { ISD::SRA, MVT::v8i64, { 1, 4, 1, 2 } }, // psraq
727 CostTableLookup(AVX512UniformCostTable, ISD, LT.second))
733 { ISD::SHL, MVT::v16i8, { 3, 5, 5, 7 } }, // psllw + pand.
734 { ISD::SRL, MVT::v16i8, { 3, 9, 5, 8 } }, // psrlw + pand.
735 { ISD::SRA, MVT::v16i8, { 4, 5, 9,13 } }, // psrlw, pand, pxor, psubb.
736 { ISD::SHL, MVT::v32i8, { 4, 7, 6, 8 } }, // psllw + pand.
737 { ISD::SRL, MVT::v32i8, { 4, 8, 7, 9 } }, // psrlw + pand.
738 { ISD::SRA, MVT::v32i8, { 6, 9,11,16 } }, // psrlw, pand, pxor, psubb.
740 { ISD::SHL, MVT::v8i16, { 1, 2, 1, 2 } }, // psllw.
741 { ISD::SRL, MVT::v8i16, { 1, 2, 1, 2 } }, // psrlw.
742 { ISD::SRA, MVT::v8i16, { 1, 2, 1, 2 } }, // psraw.
743 { ISD::SHL, MVT::v16i16, { 2, 4, 2, 3 } }, // psllw.
744 { ISD::SRL, MVT::v16i16, { 2, 4, 2, 3 } }, // psrlw.
745 { ISD::SRA, MVT::v16i16, { 2, 4, 2, 3 } }, // psraw.
747 { ISD::SHL, MVT::v4i32, { 1, 2, 1, 2 } }, // pslld
748 { ISD::SRL, MVT::v4i32, { 1, 2, 1, 2 } }, // psrld
749 { ISD::SRA, MVT::v4i32, { 1, 2, 1, 2 } }, // psrad
750 { ISD::SHL, MVT::v8i32, { 2, 4, 2, 3 } }, // pslld
751 { ISD::SRL, MVT::v8i32, { 2, 4, 2, 3 } }, // psrld
752 { ISD::SRA, MVT::v8i32, { 2, 4, 2, 3 } }, // psrad
754 { ISD::SHL, MVT::v2i64, { 1, 2, 1, 2 } }, // psllq
755 { ISD::SRL, MVT::v2i64, { 1, 2, 1, 2 } }, // psrlq
756 { ISD::SRA, MVT::v2i64, { 2, 4, 5, 7 } }, // 2 x psrad + shuffle.
757 { ISD::SHL, MVT::v4i64, { 2, 4, 1, 2 } }, // psllq
758 { ISD::SRL, MVT::v4i64, { 2, 4, 1, 2 } }, // psrlq
759 { ISD::SRA, MVT::v4i64, { 4, 6, 5, 9 } }, // 2 x psrad + shuffle.
764 CostTableLookup(AVX2UniformCostTable, ISD, LT.second))
769 { ISD::SHL, MVT::v16i8, { 4, 4, 6, 8 } }, // psllw + pand.
770 { ISD::SRL, MVT::v16i8, { 4, 8, 5, 8 } }, // psrlw + pand.
771 { ISD::SRA, MVT::v16i8, { 6, 6, 9,13 } }, // psrlw, pand, pxor, psubb.
772 { ISD::SHL, MVT::v32i8, { 7, 8,11,14 } }, // psllw + pand + split.
773 { ISD::SRL, MVT::v32i8, { 7, 9,10,14 } }, // psrlw + pand + split.
774 { ISD::SRA, MVT::v32i8, { 10,11,16,21 } }, // psrlw, pand, pxor, psubb + split.
776 { ISD::SHL, MVT::v8i16, { 1, 3, 1, 2 } }, // psllw.
777 { ISD::SRL, MVT::v8i16, { 1, 3, 1, 2 } }, // psrlw.
778 { ISD::SRA, MVT::v8i16, { 1, 3, 1, 2 } }, // psraw.
779 { ISD::SHL, MVT::v16i16, { 3, 7, 5, 7 } }, // psllw + split.
780 { ISD::SRL, MVT::v16i16, { 3, 7, 5, 7 } }, // psrlw + split.
781 { ISD::SRA, MVT::v16i16, { 3, 7, 5, 7 } }, // psraw + split.
783 { ISD::SHL, MVT::v4i32, { 1, 3, 1, 2 } }, // pslld.
784 { ISD::SRL, MVT::v4i32, { 1, 3, 1, 2 } }, // psrld.
785 { ISD::SRA, MVT::v4i32, { 1, 3, 1, 2 } }, // psrad.
786 { ISD::SHL, MVT::v8i32, { 3, 7, 5, 7 } }, // pslld + split.
787 { ISD::SRL, MVT::v8i32, { 3, 7, 5, 7 } }, // psrld + split.
788 { ISD::SRA, MVT::v8i32, { 3, 7, 5, 7 } }, // psrad + split.
790 { ISD::SHL, MVT::v2i64, { 1, 3, 1, 2 } }, // psllq.
791 { ISD::SRL, MVT::v2i64, { 1, 3, 1, 2 } }, // psrlq.
792 { ISD::SRA, MVT::v2i64, { 3, 4, 5, 7 } }, // 2 x psrad + shuffle.
793 { ISD::SHL, MVT::v4i64, { 3, 7, 4, 6 } }, // psllq + split.
794 { ISD::SRL, MVT::v4i64, { 3, 7, 4, 6 } }, // psrlq + split.
795 { ISD::SRA, MVT::v4i64, { 6, 7,10,13 } }, // 2 x (2 x psrad + shuffle) + split.
802 CostTableLookup(AVXUniformCostTable, ISD, LT.second))
808 { ISD::SHL, MVT::v16i8, { 9, 10, 6, 9 } }, // psllw + pand.
809 { ISD::SRL, MVT::v16i8, { 9, 13, 5, 9 } }, // psrlw + pand.
810 { ISD::SRA, MVT::v16i8, { 11, 15, 9,13 } }, // pcmpgtb sequence.
812 { ISD::SHL, MVT::v8i16, { 2, 2, 1, 2 } }, // psllw.
813 { ISD::SRL, MVT::v8i16, { 2, 2, 1, 2 } }, // psrlw.
814 { ISD::SRA, MVT::v8i16, { 2, 2, 1, 2 } }, // psraw.
816 { ISD::SHL, MVT::v4i32, { 2, 2, 1, 2 } }, // pslld
817 { ISD::SRL, MVT::v4i32, { 2, 2, 1, 2 } }, // psrld.
818 { ISD::SRA, MVT::v4i32, { 2, 2, 1, 2 } }, // psrad.
820 { ISD::SHL, MVT::v2i64, { 2, 2, 1, 2 } }, // psllq.
821 { ISD::SRL, MVT::v2i64, { 2, 2, 1, 2 } }, // psrlq.
822 { ISD::SRA, MVT::v2i64, { 5, 9, 5, 7 } }, // 2*psrlq + xor + sub.
828 CostTableLookup(SSE2UniformCostTable, ISD, LT.second))
833 { ISD::MUL, MVT::v2i64, { 2, 15, 1, 3 } }, // pmullq
834 { ISD::MUL, MVT::v4i64, { 2, 15, 1, 3 } }, // pmullq
835 { ISD::MUL, MVT::v8i64, { 3, 15, 1, 3 } } // pmullq
840 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second))
845 { ISD::SHL, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsllvw/pack sequence.
846 { ISD::SRL, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsrlvw/pack sequence.
847 { ISD::SRA, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsravw/pack sequence.
848 { ISD::SHL, MVT::v32i8, { 4, 23,11,16 } }, // extend/vpsllvw/pack sequence.
849 { ISD::SRL, MVT::v32i8, { 4, 30,12,18 } }, // extend/vpsrlvw/pack sequence.
850 { ISD::SRA, MVT::v32i8, { 6, 13,24,30 } }, // extend/vpsravw/pack sequence.
851 { ISD::SHL, MVT::v64i8, { 6, 19,13,15 } }, // extend/vpsllvw/pack sequence.
852 { ISD::SRL, MVT::v64i8, { 7, 27,15,18 } }, // extend/vpsrlvw/pack sequence.
853 { ISD::SRA, MVT::v64i8, { 15, 15,30,30 } }, // extend/vpsravw/pack sequence.
855 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsllvw
856 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsrlvw
857 { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsravw
858 { ISD::SHL, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsllvw
859 { ISD::SRL, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsrlvw
860 { ISD::SRA, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsravw
861 { ISD::SHL, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsllvw
862 { ISD::SRL, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsrlvw
863 { ISD::SRA, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsravw
865 { ISD::ADD, MVT::v64i8, { 1, 1, 1, 1 } }, // paddb
866 { ISD::ADD, MVT::v32i16, { 1, 1, 1, 1 } }, // paddw
868 { ISD::ADD, MVT::v32i8, { 1, 1, 1, 1 } }, // paddb
869 { ISD::ADD, MVT::v16i16, { 1, 1, 1, 1 } }, // paddw
870 { ISD::ADD, MVT::v8i32, { 1, 1, 1, 1 } }, // paddd
871 { ISD::ADD, MVT::v4i64, { 1, 1, 1, 1 } }, // paddq
873 { ISD::SUB, MVT::v64i8, { 1, 1, 1, 1 } }, // psubb
874 { ISD::SUB, MVT::v32i16, { 1, 1, 1, 1 } }, // psubw
876 { ISD::MUL, MVT::v16i8, { 4, 12, 4, 5 } }, // extend/pmullw/trunc
877 { ISD::MUL, MVT::v32i8, { 3, 10, 7,10 } }, // pmaddubsw
878 { ISD::MUL, MVT::v64i8, { 3, 11, 7,10 } }, // pmaddubsw
879 { ISD::MUL, MVT::v32i16, { 1, 5, 1, 1 } }, // pmullw
881 { ISD::SUB, MVT::v32i8, { 1, 1, 1, 1 } }, // psubb
882 { ISD::SUB, MVT::v16i16, { 1, 1, 1, 1 } }, // psubw
883 { ISD::SUB, MVT::v8i32, { 1, 1, 1, 1 } }, // psubd
884 { ISD::SUB, MVT::v4i64, { 1, 1, 1, 1 } }, // psubq
889 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second))
894 { ISD::SHL, MVT::v64i8, { 15, 19,27,33 } }, // vpblendv+split sequence.
895 { ISD::SRL, MVT::v64i8, { 15, 19,30,36 } }, // vpblendv+split sequence.
896 { ISD::SRA, MVT::v64i8, { 37, 37,51,63 } }, // vpblendv+split sequence.
898 { ISD::SHL, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsrlvd/pack sequence.
899 { ISD::SRL, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsrlvd/pack sequence.
900 { ISD::SRA, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsravd/pack sequence.
902 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } },
903 { ISD::SRL, MVT::v4i32, { 1, 1, 1, 1 } },
904 { ISD::SRA, MVT::v4i32, { 1, 1, 1, 1 } },
905 { ISD::SHL, MVT::v8i32, { 1, 1, 1, 1 } },
906 { ISD::SRL, MVT::v8i32, { 1, 1, 1, 1 } },
907 { ISD::SRA, MVT::v8i32, { 1, 1, 1, 1 } },
908 { ISD::SHL, MVT::v16i32, { 1, 1, 1, 1 } },
909 { ISD::SRL, MVT::v16i32, { 1, 1, 1, 1 } },
910 { ISD::SRA, MVT::v16i32, { 1, 1, 1, 1 } },
912 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } },
913 { ISD::SRL, MVT::v2i64, { 1, 1, 1, 1 } },
914 { ISD::SRA, MVT::v2i64, { 1, 1, 1, 1 } },
915 { ISD::SHL, MVT::v4i64, { 1, 1, 1, 1 } },
916 { ISD::SRL, MVT::v4i64, { 1, 1, 1, 1 } },
917 { ISD::SRA, MVT::v4i64, { 1, 1, 1, 1 } },
918 { ISD::SHL, MVT::v8i64, { 1, 1, 1, 1 } },
919 { ISD::SRL, MVT::v8i64, { 1, 1, 1, 1 } },
920 { ISD::SRA, MVT::v8i64, { 1, 1, 1, 1 } },
922 { ISD::ADD, MVT::v64i8, { 3, 7, 5, 5 } }, // 2*paddb + split
923 { ISD::ADD, MVT::v32i16, { 3, 7, 5, 5 } }, // 2*paddw + split
925 { ISD::SUB, MVT::v64i8, { 3, 7, 5, 5 } }, // 2*psubb + split
926 { ISD::SUB, MVT::v32i16, { 3, 7, 5, 5 } }, // 2*psubw + split
928 { ISD::AND, MVT::v32i8, { 1, 1, 1, 1 } },
929 { ISD::AND, MVT::v16i16, { 1, 1, 1, 1 } },
930 { ISD::AND, MVT::v8i32, { 1, 1, 1, 1 } },
931 { ISD::AND, MVT::v4i64, { 1, 1, 1, 1 } },
933 { ISD::OR, MVT::v32i8, { 1, 1, 1, 1 } },
934 { ISD::OR, MVT::v16i16, { 1, 1, 1, 1 } },
935 { ISD::OR, MVT::v8i32, { 1, 1, 1, 1 } },
936 { ISD::OR, MVT::v4i64, { 1, 1, 1, 1 } },
938 { ISD::XOR, MVT::v32i8, { 1, 1, 1, 1 } },
939 { ISD::XOR, MVT::v16i16, { 1, 1, 1, 1 } },
940 { ISD::XOR, MVT::v8i32, { 1, 1, 1, 1 } },
941 { ISD::XOR, MVT::v4i64, { 1, 1, 1, 1 } },
943 { ISD::MUL, MVT::v16i32, { 1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
944 { ISD::MUL, MVT::v8i32, { 1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
945 { ISD::MUL, MVT::v4i32, { 1, 10, 1, 2 } }, // pmulld (Skylake from agner.org)
946 { ISD::MUL, MVT::v8i64, { 6, 9, 8, 8 } }, // 3*pmuludq/3*shift/2*add
947 { ISD::MUL, MVT::i64, { 1 } }, // Skylake from http://www.agner.org/
951 { ISD::FNEG, MVT::v8f64, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/
952 { ISD::FADD, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
953 { ISD::FADD, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
954 { ISD::FSUB, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
955 { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
956 { ISD::FMUL, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
957 { ISD::FMUL, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
958 { ISD::FMUL, MVT::v2f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
959 { ISD::FMUL, MVT::f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
961 { ISD::FDIV, MVT::f64, { 4, 14, 1, 1 } }, // Skylake from http://www.agner.org/
962 { ISD::FDIV, MVT::v2f64, { 4, 14, 1, 1 } }, // Skylake from http://www.agner.org/
963 { ISD::FDIV, MVT::v4f64, { 8, 14, 1, 1 } }, // Skylake from http://www.agner.org/
964 { ISD::FDIV, MVT::v8f64, { 16, 23, 1, 3 } }, // Skylake from http://www.agner.org/
966 { ISD::FNEG, MVT::v16f32, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/
967 { ISD::FADD, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
968 { ISD::FADD, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
969 { ISD::FSUB, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
970 { ISD::FSUB, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
971 { ISD::FMUL, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
972 { ISD::FMUL, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
973 { ISD::FMUL, MVT::v4f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
974 { ISD::FMUL, MVT::f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/
976 { ISD::FDIV, MVT::f32, { 3, 11, 1, 1 } }, // Skylake from http://www.agner.org/
977 { ISD::FDIV, MVT::v4f32, { 3, 11, 1, 1 } }, // Skylake from http://www.agner.org/
978 { ISD::FDIV, MVT::v8f32, { 5, 11, 1, 1 } }, // Skylake from http://www.agner.org/
979 { ISD::FDIV, MVT::v16f32, { 10, 18, 1, 3 } }, // Skylake from http://www.agner.org/
983 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second))
990 { ISD::SHL, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsllvd (Haswell from agner.org)
991 { ISD::SRL, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsrlvd (Haswell from agner.org)
992 { ISD::SRA, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsravd (Haswell from agner.org)
993 { ISD::SHL, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsllvd (Haswell from agner.org)
994 { ISD::SRL, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsrlvd (Haswell from agner.org)
995 { ISD::SRA, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsravd (Haswell from agner.org)
996 { ISD::SHL, MVT::v2i64, { 2, 3, 1, 1 } }, // vpsllvq (Haswell from agner.org)
997 { ISD::SRL, MVT::v2i64, { 2, 3, 1, 1 } }, // vpsrlvq (Haswell from agner.org)
998 { ISD::SHL, MVT::v4i64, { 4, 4, 1, 2 } }, // vpsllvq (Haswell from agner.org)
999 { ISD::SRL, MVT::v4i64, { 4, 4, 1, 2 } }, // vpsrlvq (Haswell from agner.org)
1003 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && Op2Info.isConstant())
1012 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
1019 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second))
1026 { ISD::SHL, MVT::v16i8, { 1, 3, 1, 1 } },
1027 { ISD::SRL, MVT::v16i8, { 2, 3, 1, 1 } },
1028 { ISD::SRA, MVT::v16i8, { 2, 3, 1, 1 } },
1029 { ISD::SHL, MVT::v8i16, { 1, 3, 1, 1 } },
1030 { ISD::SRL, MVT::v8i16, { 2, 3, 1, 1 } },
1031 { ISD::SRA, MVT::v8i16, { 2, 3, 1, 1 } },
1032 { ISD::SHL, MVT::v4i32, { 1, 3, 1, 1 } },
1033 { ISD::SRL, MVT::v4i32, { 2, 3, 1, 1 } },
1034 { ISD::SRA, MVT::v4i32, { 2, 3, 1, 1 } },
1035 { ISD::SHL, MVT::v2i64, { 1, 3, 1, 1 } },
1036 { ISD::SRL, MVT::v2i64, { 2, 3, 1, 1 } },
1037 { ISD::SRA, MVT::v2i64, { 2, 3, 1, 1 } },
1039 { ISD::SHL, MVT::v32i8, { 4, 7, 5, 6 } },
1040 { ISD::SRL, MVT::v32i8, { 6, 7, 5, 6 } },
1041 { ISD::SRA, MVT::v32i8, { 6, 7, 5, 6 } },
1042 { ISD::SHL, MVT::v16i16, { 4, 7, 5, 6 } },
1043 { ISD::SRL, MVT::v16i16, { 6, 7, 5, 6 } },
1044 { ISD::SRA, MVT::v16i16, { 6, 7, 5, 6 } },
1045 { ISD::SHL, MVT::v8i32, { 4, 7, 5, 6 } },
1046 { ISD::SRL, MVT::v8i32, { 6, 7, 5, 6 } },
1047 { ISD::SRA, MVT::v8i32, { 6, 7, 5, 6 } },
1048 { ISD::SHL, MVT::v4i64, { 4, 7, 5, 6 } },
1049 { ISD::SRL, MVT::v4i64, { 6, 7, 5, 6 } },
1050 { ISD::SRA, MVT::v4i64, { 6, 7, 5, 6 } },
1057 int ShiftISD = ISD;
1058 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && Op2Info.isConstant())
1059 ShiftISD = ISD::SHL;
1066 if (ISD == ISD::SHL && !Op2Info.isUniform() && Op2Info.isConstant()) {
1072 ISD = ISD::MUL;
1076 { ISD::FDIV, MVT::f32, { 18, 19, 1, 1 } }, // divss
1077 { ISD::FDIV, MVT::v4f32, { 35, 36, 1, 1 } }, // divps
1078 { ISD::FDIV, MVT::f64, { 33, 34, 1, 1 } }, // divsd
1079 { ISD::FDIV, MVT::v2f64, { 65, 66, 1, 1 } }, // divpd
1083 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, LT.second))
1088 { ISD::MUL, MVT::v4i32, { 11, 11, 1, 7 } }, // pmulld
1089 { ISD::MUL, MVT::v8i16, { 2, 5, 1, 1 } }, // pmullw
1090 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // mulsd
1091 { ISD::FMUL, MVT::f32, { 1, 4, 1, 1 } }, // mulss
1092 { ISD::FMUL, MVT::v2f64, { 4, 7, 1, 1 } }, // mulpd
1093 { ISD::FMUL, MVT::v4f32, { 2, 5, 1, 1 } }, // mulps
1094 { ISD::FDIV, MVT::f32, { 17, 19, 1, 1 } }, // divss
1095 { ISD::FDIV, MVT::v4f32, { 39, 39, 1, 6 } }, // divps
1096 { ISD::FDIV, MVT::f64, { 32, 34, 1, 1 } }, // divsd
1097 { ISD::FDIV, MVT::v2f64, { 69, 69, 1, 6 } }, // divpd
1098 { ISD::FADD, MVT::v2f64, { 2, 4, 1, 1 } }, // addpd
1099 { ISD::FSUB, MVT::v2f64, { 2, 4, 1, 1 } }, // subpd
1105 { ISD::MUL, MVT::v2i64, { 17, 22, 9, 9 } },
1107 { ISD::ADD, MVT::v2i64, { 4, 2, 1, 2 } },
1108 { ISD::SUB, MVT::v2i64, { 4, 2, 1, 2 } },
1112 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, LT.second))
1117 { ISD::SHL, MVT::v16i8, { 6, 21,11,16 } }, // vpblendvb sequence.
1118 { ISD::SHL, MVT::v32i8, { 6, 23,11,22 } }, // vpblendvb sequence.
1119 { ISD::SHL, MVT::v8i16, { 5, 18, 5,10 } }, // extend/vpsrlvd/pack sequence.
1120 { ISD::SHL, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsrlvd/pack sequence.
1122 { ISD::SRL, MVT::v16i8, { 6, 27,12,18 } }, // vpblendvb sequence.
1123 { ISD::SRL, MVT::v32i8, { 8, 30,12,24 } }, // vpblendvb sequence.
1124 { ISD::SRL, MVT::v8i16, { 5, 11, 5,10 } }, // extend/vpsrlvd/pack sequence.
1125 { ISD::SRL, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsrlvd/pack sequence.
1127 { ISD::SRA, MVT::v16i8, { 17, 17,24,30 } }, // vpblendvb sequence.
1128 { ISD::SRA, MVT::v32i8, { 18, 20,24,43 } }, // vpblendvb sequence.
1129 { ISD::SRA, MVT::v8i16, { 5, 11, 5,10 } }, // extend/vpsravd/pack sequence.
1130 { ISD::SRA, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsravd/pack sequence.
1131 { ISD::SRA, MVT::v2i64, { 4, 5, 5, 5 } }, // srl/xor/sub sequence.
1132 { ISD::SRA, MVT::v4i64, { 8, 8, 5, 9 } }, // srl/xor/sub sequence.
1134 { ISD::SUB, MVT::v32i8, { 1, 1, 1, 2 } }, // psubb
1135 { ISD::ADD, MVT::v32i8, { 1, 1, 1, 2 } }, // paddb
1136 { ISD::SUB, MVT::v16i16, { 1, 1, 1, 2 } }, // psubw
1137 { ISD::ADD, MVT::v16i16, { 1, 1, 1, 2 } }, // paddw
1138 { ISD::SUB, MVT::v8i32, { 1, 1, 1, 2 } }, // psubd
1139 { ISD::ADD, MVT::v8i32, { 1, 1, 1, 2 } }, // paddd
1140 { ISD::SUB, MVT::v4i64, { 1, 1, 1, 2 } }, // psubq
1141 { ISD::ADD, MVT::v4i64, { 1, 1, 1, 2 } }, // paddq
1143 { ISD::MUL, MVT::v16i8, { 5, 18, 6,12 } }, // extend/pmullw/pack
1144 { ISD::MUL, MVT::v32i8, { 4, 8, 8,16 } }, // pmaddubsw
1145 { ISD::MUL, MVT::v16i16, { 2, 5, 1, 2 } }, // pmullw
1146 { ISD::MUL, MVT::v8i32, { 4, 10, 1, 2 } }, // pmulld
1147 { ISD::MUL, MVT::v4i32, { 2, 10, 1, 2 } }, // pmulld
1148 { ISD::MUL, MVT::v4i64, { 6, 10, 8,13 } }, // 3*pmuludq/3*shift/2*add
1149 { ISD::MUL, MVT::v2i64, { 6, 10, 8, 8 } }, // 3*pmuludq/3*shift/2*add
1153 { ISD::FNEG, MVT::v4f64, { 1, 1, 1, 2 } }, // vxorpd
1154 { ISD::FNEG, MVT::v8f32, { 1, 1, 1, 2 } }, // vxorps
1156 { ISD::FADD, MVT::f64, { 1, 4, 1, 1 } }, // vaddsd
1157 { ISD::FADD, MVT::f32, { 1, 4, 1, 1 } }, // vaddss
1158 { ISD::FADD, MVT::v2f64, { 1, 4, 1, 1 } }, // vaddpd
1159 { ISD::FADD, MVT::v4f32, { 1, 4, 1, 1 } }, // vaddps
1160 { ISD::FADD, MVT::v4f64, { 1, 4, 1, 2 } }, // vaddpd
1161 { ISD::FADD, MVT::v8f32, { 1, 4, 1, 2 } }, // vaddps
1163 { ISD::FSUB, MVT::f64, { 1, 4, 1, 1 } }, // vsubsd
1164 { ISD::FSUB, MVT::f32, { 1, 4, 1, 1 } }, // vsubss
1165 { ISD::FSUB, MVT::v2f64, { 1, 4, 1, 1 } }, // vsubpd
1166 { ISD::FSUB, MVT::v4f32, { 1, 4, 1, 1 } }, // vsubps
1167 { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 2 } }, // vsubpd
1168 { ISD::FSUB, MVT::v8f32, { 1, 4, 1, 2 } }, // vsubps
1170 { ISD::FMUL, MVT::f64, { 1, 5, 1, 1 } }, // vmulsd
1171 { ISD::FMUL, MVT::f32, { 1, 5, 1, 1 } }, // vmulss
1172 { ISD::FMUL, MVT::v2f64, { 1, 5, 1, 1 } }, // vmulpd
1173 { ISD::FMUL, MVT::v4f32, { 1, 5, 1, 1 } }, // vmulps
1174 { ISD::FMUL, MVT::v4f64, { 1, 5, 1, 2 } }, // vmulpd
1175 { ISD::FMUL, MVT::v8f32, { 1, 5, 1, 2 } }, // vmulps
1177 { ISD::FDIV, MVT::f32, { 7, 13, 1, 1 } }, // vdivss
1178 { ISD::FDIV, MVT::v4f32, { 7, 13, 1, 1 } }, // vdivps
1179 { ISD::FDIV, MVT::v8f32, { 14, 21, 1, 3 } }, // vdivps
1180 { ISD::FDIV, MVT::f64, { 14, 20, 1, 1 } }, // vdivsd
1181 { ISD::FDIV, MVT::v2f64, { 14, 20, 1, 1 } }, // vdivpd
1182 { ISD::FDIV, MVT::v4f64, { 28, 35, 1, 3 } }, // vdivpd
1187 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second))
1195 { ISD::MUL, MVT::v32i8, { 10, 11, 18, 19 } }, // pmaddubsw + split
1196 { ISD::MUL, MVT::v16i8, { 5, 6, 8, 12 } }, // 2*pmaddubsw/3*and/psllw/or
1197 { ISD::MUL, MVT::v16i16, { 4, 8, 5, 6 } }, // pmullw + split
1198 { ISD::MUL, MVT::v8i32, { 5, 8, 5, 10 } }, // pmulld + split
1199 { ISD::MUL, MVT::v4i32, { 2, 5, 1, 3 } }, // pmulld
1200 { ISD::MUL, MVT::v4i64, { 12, 15, 19, 20 } },
1202 { ISD::AND, MVT::v32i8, { 1, 1, 1, 2 } }, // vandps
1203 { ISD::AND, MVT::v16i16, { 1, 1, 1, 2 } }, // vandps
1204 { ISD::AND, MVT::v8i32, { 1, 1, 1, 2 } }, // vandps
1205 { ISD::AND, MVT::v4i64, { 1, 1, 1, 2 } }, // vandps
1207 { ISD::OR, MVT::v32i8, { 1, 1, 1, 2 } }, // vorps
1208 { ISD::OR, MVT::v16i16, { 1, 1, 1, 2 } }, // vorps
1209 { ISD::OR, MVT::v8i32, { 1, 1, 1, 2 } }, // vorps
1210 { ISD::OR, MVT::v4i64, { 1, 1, 1, 2 } }, // vorps
1212 { ISD::XOR, MVT::v32i8, { 1, 1, 1, 2 } }, // vxorps
1213 { ISD::XOR, MVT::v16i16, { 1, 1, 1, 2 } }, // vxorps
1214 { ISD::XOR, MVT::v8i32, { 1, 1, 1, 2 } }, // vxorps
1215 { ISD::XOR, MVT::v4i64, { 1, 1, 1, 2 } }, // vxorps
1217 { ISD::SUB, MVT::v32i8, { 4, 2, 5, 6 } }, // psubb + split
1218 { ISD::ADD, MVT::v32i8, { 4, 2, 5, 6 } }, // paddb + split
1219 { ISD::SUB, MVT::v16i16, { 4, 2, 5, 6 } }, // psubw + split
1220 { ISD::ADD, MVT::v16i16, { 4, 2, 5, 6 } }, // paddw + split
1221 { ISD::SUB, MVT::v8i32, { 4, 2, 5, 6 } }, // psubd + split
1222 { ISD::ADD, MVT::v8i32, { 4, 2, 5, 6 } }, // paddd + split
1223 { ISD::SUB, MVT::v4i64, { 4, 2, 5, 6 } }, // psubq + split
1224 { ISD::ADD, MVT::v4i64, { 4, 2, 5, 6 } }, // paddq + split
1225 { ISD::SUB, MVT::v2i64, { 1, 1, 1, 1 } }, // psubq
1226 { ISD::ADD, MVT::v2i64, { 1, 1, 1, 1 } }, // paddq
1228 { ISD::SHL, MVT::v16i8, { 10, 21,11,17 } }, // pblendvb sequence.
1229 { ISD::SHL, MVT::v32i8, { 22, 22,27,40 } }, // pblendvb sequence + split.
1230 { ISD::SHL, MVT::v8i16, { 6, 9,11,11 } }, // pblendvb sequence.
1231 { ISD::SHL, MVT::v16i16, { 13, 16,24,25 } }, // pblendvb sequence + split.
1232 { ISD::SHL, MVT::v4i32, { 3, 11, 4, 6 } }, // pslld/paddd/cvttps2dq/pmulld
1233 { ISD::SHL, MVT::v8i32, { 9, 11,12,17 } }, // pslld/paddd/cvttps2dq/pmulld + split
1234 { ISD::SHL, MVT::v2i64, { 2, 4, 4, 6 } }, // Shift each lane + blend.
1235 { ISD::SHL, MVT::v4i64, { 6, 7,11,15 } }, // Shift each lane + blend + split.
1237 { ISD::SRL, MVT::v16i8, { 11, 27,12,18 } }, // pblendvb sequence.
1238 { ISD::SRL, MVT::v32i8, { 23, 23,30,43 } }, // pblendvb sequence + split.
1239 { ISD::SRL, MVT::v8i16, { 13, 16,14,22 } }, // pblendvb sequence.
1240 { ISD::SRL, MVT::v16i16, { 28, 30,31,48 } }, // pblendvb sequence + split.
1241 { ISD::SRL, MVT::v4i32, { 6, 7,12,16 } }, // Shift each lane + blend.
1242 { ISD::SRL, MVT::v8i32, { 14, 14,26,34 } }, // Shift each lane + blend + split.
1243 { ISD::SRL, MVT::v2i64, { 2, 4, 4, 6 } }, // Shift each lane + blend.
1244 { ISD::SRL, MVT::v4i64, { 6, 7,11,15 } }, // Shift each lane + blend + split.
1246 { ISD::SRA, MVT::v16i8, { 21, 22,24,36 } }, // pblendvb sequence.
1247 { ISD::SRA, MVT::v32i8, { 44, 45,51,76 } }, // pblendvb sequence + split.
1248 { ISD::SRA, MVT::v8i16, { 13, 16,14,22 } }, // pblendvb sequence.
1249 { ISD::SRA, MVT::v16i16, { 28, 30,31,48 } }, // pblendvb sequence + split.
1250 { ISD::SRA, MVT::v4i32, { 6, 7,12,16 } }, // Shift each lane + blend.
1251 { ISD::SRA, MVT::v8i32, { 14, 14,26,34 } }, // Shift each lane + blend + split.
1252 { ISD::SRA, MVT::v2i64, { 5, 6,10,14 } }, // Shift each lane + blend.
1253 { ISD::SRA, MVT::v4i64, { 12, 12,22,30 } }, // Shift each lane + blend + split.
1255 { ISD::FNEG, MVT::v4f64, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/
1256 { ISD::FNEG, MVT::v8f32, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/
1258 { ISD::FADD, MVT::f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1259 { ISD::FADD, MVT::f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1260 { ISD::FADD, MVT::v2f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1261 { ISD::FADD, MVT::v4f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1262 { ISD::FADD, MVT::v4f64, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1263 { ISD::FADD, MVT::v8f32, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1265 { ISD::FSUB, MVT::f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1266 { ISD::FSUB, MVT::f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1267 { ISD::FSUB, MVT::v2f64, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1268 { ISD::FSUB, MVT::v4f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/
1269 { ISD::FSUB, MVT::v4f64, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1270 { ISD::FSUB, MVT::v8f32, { 2, 5, 1, 2 } }, // BDVER2 from http://www.agner.org/
1272 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1273 { ISD::FMUL, MVT::f32, { 1, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1274 { ISD::FMUL, MVT::v2f64, { 2, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1275 { ISD::FMUL, MVT::v4f32, { 1, 5, 1, 1 } }, // BTVER2 from http://www.agner.org/
1276 { ISD::FMUL, MVT::v4f64, { 4, 5, 1, 2 } }, // BTVER2 from http://www.agner.org/
1277 { ISD::FMUL, MVT::v8f32, { 2, 5, 1, 2 } }, // BTVER2 from http://www.agner.org/
1279 { ISD::FDIV, MVT::f32, { 14, 14, 1, 1 } }, // SNB from http://www.agner.org/
1280 { ISD::FDIV, MVT::v4f32, { 14, 14, 1, 1 } }, // SNB from http://www.agner.org/
1281 { ISD::FDIV, MVT::v8f32, { 28, 29, 1, 3 } }, // SNB from http://www.agner.org/
1282 { ISD::FDIV, MVT::f64, { 22, 22, 1, 1 } }, // SNB from http://www.agner.org/
1283 { ISD::FDIV, MVT::v2f64, { 22, 22, 1, 1 } }, // SNB from http://www.agner.org/
1284 { ISD::FDIV, MVT::v4f64, { 44, 45, 1, 3 } }, // SNB from http://www.agner.org/
1288 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second))
1293 { ISD::FADD, MVT::f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1294 { ISD::FADD, MVT::f32, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1295 { ISD::FADD, MVT::v2f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1296 { ISD::FADD, MVT::v4f32, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1298 { ISD::FSUB, MVT::f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1299 { ISD::FSUB, MVT::f32 , { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1300 { ISD::FSUB, MVT::v2f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1301 { ISD::FSUB, MVT::v4f32, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/
1303 { ISD::FMUL, MVT::f64, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1304 { ISD::FMUL, MVT::f32, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1305 { ISD::FMUL, MVT::v2f64, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1306 { ISD::FMUL, MVT::v4f32, { 1, 5, 1, 1 } }, // Nehalem from http://www.agner.org/
1308 { ISD::FDIV, MVT::f32, { 14, 14, 1, 1 } }, // Nehalem from http://www.agner.org/
1309 { ISD::FDIV, MVT::v4f32, { 14, 14, 1, 1 } }, // Nehalem from http://www.agner.org/
1310 { ISD::FDIV, MVT::f64, { 22, 22, 1, 1 } }, // Nehalem from http://www.agner.org/
1311 { ISD::FDIV, MVT::v2f64, { 22, 22, 1, 1 } }, // Nehalem from http://www.agner.org/
1313 { ISD::MUL, MVT::v2i64, { 6, 10,10,10 } } // 3*pmuludq/3*shift/2*add
1317 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second))
1322 { ISD::SHL, MVT::v16i8, { 15, 24,17,22 } }, // pblendvb sequence.
1323 { ISD::SHL, MVT::v8i16, { 11, 14,11,11 } }, // pblendvb sequence.
1324 { ISD::SHL, MVT::v4i32, { 14, 20, 4,10 } }, // pslld/paddd/cvttps2dq/pmulld
1326 { ISD::SRL, MVT::v16i8, { 16, 27,18,24 } }, // pblendvb sequence.
1327 { ISD::SRL, MVT::v8i16, { 22, 26,23,27 } }, // pblendvb sequence.
1328 { ISD::SRL, MVT::v4i32, { 16, 17,15,19 } }, // Shift each lane + blend.
1329 { ISD::SRL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence.
1331 { ISD::SRA, MVT::v16i8, { 38, 41,30,36 } }, // pblendvb sequence.
1332 { ISD::SRA, MVT::v8i16, { 22, 26,23,27 } }, // pblendvb sequence.
1333 { ISD::SRA, MVT::v4i32, { 16, 17,15,19 } }, // Shift each lane + blend.
1334 { ISD::SRA, MVT::v2i64, { 8, 17, 5, 7 } }, // splat+shuffle sequence.
1336 { ISD::MUL, MVT::v4i32, { 2, 11, 1, 1 } } // pmulld (Nehalem from agner.org)
1340 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second))
1345 { ISD::MUL, MVT::v16i8, { 5, 18,10,12 } }, // 2*pmaddubsw/3*and/psllw/or
1349 if (const auto *Entry = CostTableLookup(SSSE3CostTable, ISD, LT.second))
1356 { ISD::SHL, MVT::v16i8, { 13, 21,26,28 } }, // cmpgtb sequence.
1357 { ISD::SHL, MVT::v8i16, { 24, 27,16,20 } }, // cmpgtw sequence.
1358 { ISD::SHL, MVT::v4i32, { 17, 19,10,12 } }, // pslld/paddd/cvttps2dq/pmuludq.
1359 { ISD::SHL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence.
1361 { ISD::SRL, MVT::v16i8, { 14, 28,27,30 } }, // cmpgtb sequence.
1362 { ISD::SRL, MVT::v8i16, { 16, 19,31,31 } }, // cmpgtw sequence.
1363 { ISD::SRL, MVT::v4i32, { 12, 12,15,19 } }, // Shift each lane + blend.
1364 { ISD::SRL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence.
1366 { ISD::SRA, MVT::v16i8, { 27, 30,54,54 } }, // unpacked cmpgtb sequence.
1367 { ISD::SRA, MVT::v8i16, { 16, 19,31,31 } }, // cmpgtw sequence.
1368 { ISD::SRA, MVT::v4i32, { 12, 12,15,19 } }, // Shift each lane + blend.
1369 { ISD::SRA, MVT::v2i64, { 8, 11,12,16 } }, // srl/xor/sub splat+shuffle sequence.
1371 { ISD::AND, MVT::v16i8, { 1, 1, 1, 1 } }, // pand
1372 { ISD::AND, MVT::v8i16, { 1, 1, 1, 1 } }, // pand
1373 { ISD::AND, MVT::v4i32, { 1, 1, 1, 1 } }, // pand
1374 { ISD::AND, MVT::v2i64, { 1, 1, 1, 1 } }, // pand
1376 { ISD::OR, MVT::v16i8, { 1, 1, 1, 1 } }, // por
1377 { ISD::OR, MVT::v8i16, { 1, 1, 1, 1 } }, // por
1378 { ISD::OR, MVT::v4i32, { 1, 1, 1, 1 } }, // por
1379 { ISD::OR, MVT::v2i64, { 1, 1, 1, 1 } }, // por
1381 { ISD::XOR, MVT::v16i8, { 1, 1, 1, 1 } }, // pxor
1382 { ISD::XOR, MVT::v8i16, { 1, 1, 1, 1 } }, // pxor
1383 { ISD::XOR, MVT::v4i32, { 1, 1, 1, 1 } }, // pxor
1384 { ISD::XOR, MVT::v2i64, { 1, 1, 1, 1 } }, // pxor
1386 { ISD::ADD, MVT::v2i64, { 1, 2, 1, 2 } }, // paddq
1387 { ISD::SUB, MVT::v2i64, { 1, 2, 1, 2 } }, // psubq
1389 { ISD::MUL, MVT::v16i8, { 6, 18,12,12 } }, // 2*unpack/2*pmullw/2*and/pack
1390 { ISD::MUL, MVT::v8i16, { 1, 5, 1, 1 } }, // pmullw
1391 { ISD::MUL, MVT::v4i32, { 6, 8, 7, 7 } }, // 3*pmuludq/4*shuffle
1392 { ISD::MUL, MVT::v2i64, { 7, 10,10,10 } }, // 3*pmuludq/3*shift/2*add
1396 { ISD::FDIV, MVT::f32, { 23, 23, 1, 1 } }, // Pentium IV from http://www.agner.org/
1397 { ISD::FDIV, MVT::v4f32, { 39, 39, 1, 1 } }, // Pentium IV from http://www.agner.org/
1398 { ISD::FDIV, MVT::f64, { 38, 38, 1, 1 } }, // Pentium IV from http://www.agner.org/
1399 { ISD::FDIV, MVT::v2f64, { 69, 69, 1, 1 } }, // Pentium IV from http://www.agner.org/
1401 { ISD::FNEG, MVT::f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1402 { ISD::FNEG, MVT::f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1403 { ISD::FNEG, MVT::v4f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1404 { ISD::FNEG, MVT::v2f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/
1406 { ISD::FADD, MVT::f32, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1407 { ISD::FADD, MVT::f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1408 { ISD::FADD, MVT::v2f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1410 { ISD::FSUB, MVT::f32, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1411 { ISD::FSUB, MVT::f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1412 { ISD::FSUB, MVT::v2f64, { 2, 3, 1, 1 } }, // Pentium IV from http://www.agner.org/
1414 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // Pentium IV from http://www.agner.org/
1415 { ISD::FMUL, MVT::v2f64, { 2, 5, 1, 1 } }, // Pentium IV from http://www.agner.org/
1419 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second))
1424 { ISD::FDIV, MVT::f32, { 17, 18, 1, 1 } }, // Pentium III from http://www.agner.org/
1425 { ISD::FDIV, MVT::v4f32, { 34, 48, 1, 1 } }, // Pentium III from http://www.agner.org/
1427 { ISD::FNEG, MVT::f32, { 2, 2, 1, 2 } }, // Pentium III from http://www.agner.org/
1428 { ISD::FNEG, MVT::v4f32, { 2, 2, 1, 2 } }, // Pentium III from http://www.agner.org/
1430 { ISD::FADD, MVT::f32, { 1, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1431 { ISD::FADD, MVT::v4f32, { 2, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1433 { ISD::FSUB, MVT::f32, { 1, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1434 { ISD::FSUB, MVT::v4f32, { 2, 3, 1, 1 } }, // Pentium III from http://www.agner.org/
1436 { ISD::FMUL, MVT::f32, { 2, 5, 1, 1 } }, // Pentium III from http://www.agner.org/
1437 { ISD::FMUL, MVT::v4f32, { 2, 5, 1, 1 } }, // Pentium III from http://www.agner.org/
1441 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second))
1446 { ISD::ADD, MVT::i64, { 1 } }, // Core (Merom) from http://www.agner.org/
1447 { ISD::SUB, MVT::i64, { 1 } }, // Core (Merom) from http://www.agner.org/
1448 { ISD::MUL, MVT::i64, { 2, 6, 1, 2 } },
1452 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second))
1457 { ISD::ADD, MVT::i8, { 1 } }, // Pentium III from http://www.agner.org/
1458 { ISD::ADD, MVT::i16, { 1 } }, // Pentium III from http://www.agner.org/
1459 { ISD::ADD, MVT::i32, { 1 } }, // Pentium III from http://www.agner.org/
1461 { ISD::SUB, MVT::i8, { 1 } }, // Pentium III from http://www.agner.org/
1462 { ISD::SUB, MVT::i16, { 1 } }, // Pentium III from http://www.agner.org/
1463 { ISD::SUB, MVT::i32, { 1 } }, // Pentium III from http://www.agner.org/
1465 { ISD::MUL, MVT::i8, { 3, 4, 1, 1 } },
1466 { ISD::MUL, MVT::i16, { 2, 4, 1, 1 } },
1467 { ISD::MUL, MVT::i32, { 1, 4, 1, 1 } },
1469 { ISD::FNEG, MVT::f64, { 2, 2, 1, 3 } }, // (x87)
1470 { ISD::FADD, MVT::f64, { 2, 3, 1, 1 } }, // (x87)
1471 { ISD::FSUB, MVT::f64, { 2, 3, 1, 1 } }, // (x87)
1472 { ISD::FMUL, MVT::f64, { 2, 5, 1, 1 } }, // (x87)
1473 { ISD::FDIV, MVT::f64, { 38, 38, 1, 1 } }, // (x87)
1476 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second))
1487 (ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
1488 ISD == ISD::UREM)) {
1497 switch (ISD) {
1498 case ISD::FADD:
1499 case ISD::FSUB:
1500 case ISD::FMUL:
1501 case ISD::FDIV:
1502 case ISD::FNEG:
1503 case ISD::AND:
1504 case ISD::OR:
1505 case ISD::XOR:
2274 int ISD = TLI->InstructionOpcodeToISD(Opcode);
2275 assert(ISD && "Invalid opcode");
2283 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, { 1, 1, 1, 1 } },
2284 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, { 1, 1, 1, 1 } },
2287 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, { 1, 1, 1, 1 } },
2288 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, { 1, 1, 1, 1 } },
2289 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, { 1, 1, 1, 1 } },
2290 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, { 1, 1, 1, 1 } },
2291 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, { 1, 1, 1, 1 } },
2292 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, { 1, 1, 1, 1 } },
2293 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, { 1, 1, 1, 1 } },
2294 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, { 1, 1, 1, 1 } },
2295 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, { 1, 1, 1, 1 } },
2296 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, { 1, 1, 1, 1 } },
2297 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, { 1, 1, 1, 1 } },
2298 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, { 1, 1, 1, 1 } },
2299 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, { 1, 1, 1, 1 } },
2300 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, { 1, 1, 1, 1 } },
2301 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, { 1, 1, 1, 1 } },
2302 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, { 1, 1, 1, 1 } },
2303 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, { 1, 1, 1, 1 } },
2306 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, { 2, 1, 1, 1 } },
2307 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, { 2, 1, 1, 1 } },
2308 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, { 2, 1, 1, 1 } },
2309 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, { 2, 1, 1, 1 } },
2310 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, { 2, 1, 1, 1 } },
2311 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, { 2, 1, 1, 1 } },
2312 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, { 2, 1, 1, 1 } },
2313 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, { 2, 1, 1, 1 } },
2314 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, { 2, 1, 1, 1 } },
2315 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, { 2, 1, 1, 1 } },
2316 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, { 2, 1, 1, 1 } },
2317 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, { 2, 1, 1, 1 } },
2318 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, { 2, 1, 1, 1 } },
2319 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, { 2, 1, 1, 1 } },
2320 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, { 2, 1, 1, 1 } },
2321 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, { 2, 1, 1, 1 } },
2322 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, { 2, 1, 1, 1 } },
2324 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 2, 1, 1, 1 } },
2325 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, { 2, 1, 1, 1 } },
2326 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 2, 1, 1, 1 } },
2327 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, { 2, 1, 1, 1 } },
2328 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 2, 1, 1, 1 } },
2329 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, { 2, 1, 1, 1 } },
2330 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, { 2, 1, 1, 1 } },
2331 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, { 2, 1, 1, 1 } },
2332 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, { 2, 1, 1, 1 } },
2333 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, { 2, 1, 1, 1 } },
2334 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, { 2, 1, 1, 1 } },
2335 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, { 2, 1, 1, 1 } },
2336 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, { 2, 1, 1, 1 } },
2337 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, { 2, 1, 1, 1 } },
2338 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, { 2, 1, 1, 1 } },
2339 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, { 2, 1, 1, 1 } },
2340 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, { 2, 1, 1, 1 } },
2342 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, { 2, 1, 1, 1 } },
2343 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, { 2, 1, 1, 1 } }, // widen to zmm
2344 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, { 2, 1, 1, 1 } }, // vpmovwb
2345 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, { 2, 1, 1, 1 } }, // vpmovwb
2346 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, { 2, 1, 1, 1 } }, // vpmovwb
2351 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, { 1, 1, 1, 1 } },
2352 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, { 1, 1, 1, 1 } },
2353 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, { 1, 1, 1, 1 } },
2354 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 1, 1, 1, 1 } },
2355 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 1, 1, 1, 1 } },
2356 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i1, { 1, 1, 1, 1 } },
2357 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, { 1, 1, 1, 1 } },
2358 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, { 1, 1, 1, 1 } },
2361 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, { 2, 1, 1, 1, } },
2362 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, { 2, 1, 1, 1, } },
2363 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, { 2, 1, 1, 1, } },
2364 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 2, 1, 1, 1, } },
2365 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 2, 1, 1, 1, } },
2366 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i1, { 2, 1, 1, 1, } },
2367 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, { 2, 1, 1, 1, } },
2368 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, { 2, 1, 1, 1, } },
2370 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, { 2, 1, 1, 1 } },
2371 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, { 2, 1, 1, 1 } },
2372 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, { 2, 1, 1, 1 } },
2373 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, { 2, 1, 1, 1 } },
2374 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 2, 1, 1, 1 } },
2375 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, { 2, 1, 1, 1 } },
2376 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, { 2, 1, 1, 1 } },
2377 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i64, { 2, 1, 1, 1 } },
2379 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, { 1, 1, 1, 1 } },
2380 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, { 1, 1, 1, 1 } },
2382 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, { 1, 1, 1, 1 } },
2383 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, { 1, 1, 1, 1 } },
2385 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, { 1, 1, 1, 1 } },
2386 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, { 1, 1, 1, 1 } },
2388 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, { 1, 1, 1, 1 } },
2389 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, { 1, 1, 1, 1 } },
2396 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, { 1, 1, 1, 1 } },
2397 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, { 3, 1, 1, 1 } },
2398 { ISD::FP_EXTEND, MVT::v16f64, MVT::v16f32, { 4, 1, 1, 1 } }, // 2*vcvtps2pd+vextractf64x4
2399 { ISD::FP_EXTEND, MVT::v16f32, MVT::v16f16, { 1, 1, 1, 1 } }, // vcvtph2ps
2400 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f16, { 2, 1, 1, 1 } }, // vcvtph2ps+vcvtps2pd
2401 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, { 1, 1, 1, 1 } },
2402 { ISD::FP_ROUND, MVT::v16f16, MVT::v16f32, { 1, 1, 1, 1 } }, // vcvtps2ph
2404 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2405 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2406 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2407 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2408 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2409 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2410 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2411 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2412 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, { 2, 1, 1, 1 } }, // zmm vpslld+vptestmd
2413 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, { 2, 1, 1, 1 } }, // zmm vpslld+vptestmd
2414 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 2, 1, 1, 1 } }, // zmm vpslld+vptestmd
2415 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, { 2, 1, 1, 1 } }, // vpslld+vptestmd
2416 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, { 2, 1, 1, 1 } }, // zmm vpsllq+vptestmq
2417 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, { 2, 1, 1, 1 } }, // zmm vpsllq+vptestmq
2418 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, { 2, 1, 1, 1 } }, // vpsllq+vptestmq
2419 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, { 2, 1, 1, 1 } }, // vpmovdb
2420 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, { 2, 1, 1, 1 } }, // vpmovdb
2421 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, { 2, 1, 1, 1 } }, // vpmovdb
2422 { ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, { 2, 1, 1, 1 } }, // vpmovdb
2423 { ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, { 2, 1, 1, 1 } }, // vpmovdb
2424 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, { 2, 1, 1, 1 } }, // vpmovdw
2425 { ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, { 2, 1, 1, 1 } }, // vpmovdw
2426 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, { 2, 1, 1, 1 } }, // vpmovqb
2427 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, { 1, 1, 1, 1 } }, // vpshufb
2428 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqb
2429 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqb
2430 { ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqb
2431 { ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqb
2432 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqw
2433 { ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqw
2434 { ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, { 2, 1, 1, 1 } }, // vpmovqw
2435 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, { 1, 1, 1, 1 } }, // vpmovqd
2436 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, { 1, 1, 1, 1 } }, // zmm vpmovqd
2437 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, { 5, 1, 1, 1 } },// 2*vpmovqd+concat+vpmovdb
2439 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, { 3, 1, 1, 1 } }, // extend to v16i32
2440 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, { 8, 1, 1, 1 } },
2441 { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, { 8, 1, 1, 1 } },
2445 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, { 3, 1, 1, 1 } },
2446 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, { 4, 1, 1, 1 } },
2447 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, { 3, 1, 1, 1 } },
2448 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, { 4, 1, 1, 1 } },
2449 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, { 3, 1, 1, 1 } },
2450 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, { 4, 1, 1, 1 } },
2451 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, { 3, 1, 1, 1 } },
2452 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, { 4, 1, 1, 1 } },
2456 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, { 3, 1, 1, 1 } },
2457 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, { 4, 1, 1, 1 } },
2458 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, { 3, 1, 1, 1 } },
2459 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, { 4, 1, 1, 1 } },
2460 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, { 3, 1, 1, 1 } },
2461 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, { 4, 1, 1, 1 } },
2462 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, { 3, 1, 1, 1 } },
2463 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, { 4, 1, 1, 1 } },
2465 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, { 1, 1, 1, 1 } }, // zmm vpternlogd
2466 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, { 2, 1, 1, 1 } }, // zmm vpternlogd+psrld
2467 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, { 1, 1, 1, 1 } }, // zmm vpternlogd
2468 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, { 2, 1, 1, 1 } }, // zmm vpternlogd+psrld
2469 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 1, 1, 1, 1 } }, // zmm vpternlogd
2470 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 2, 1, 1, 1 } }, // zmm vpternlogd+psrld
2471 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, { 1, 1, 1, 1 } }, // zmm vpternlogq
2472 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, { 2, 1, 1, 1 } }, // zmm vpternlogq+psrlq
2473 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 1, 1, 1, 1 } }, // zmm vpternlogq
2474 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 2, 1, 1, 1 } }, // zmm vpternlogq+psrlq
2476 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, { 1, 1, 1, 1 } }, // vpternlogd
2477 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, { 2, 1, 1, 1 } }, // vpternlogd+psrld
2478 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, { 1, 1, 1, 1 } }, // vpternlogq
2479 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, { 2, 1, 1, 1 } }, // vpternlogq+psrlq
2481 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, { 1, 1, 1, 1 } },
2482 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, { 1, 1, 1, 1 } },
2483 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, { 1, 1, 1, 1 } },
2484 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, { 1, 1, 1, 1 } },
2485 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, { 1, 1, 1, 1 } },
2486 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, { 1, 1, 1, 1 } },
2487 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, { 1, 1, 1, 1 } },
2488 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, { 1, 1, 1, 1 } },
2489 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, { 1, 1, 1, 1 } },
2490 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, { 1, 1, 1, 1 } },
2492 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, { 3, 1, 1, 1 } }, // FIXME: May not be right
2493 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, { 3, 1, 1, 1 } }, // FIXME: May not be right
2495 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, { 4, 1, 1, 1 } },
2496 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, { 3, 1, 1, 1 } },
2497 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, { 2, 1, 1, 1 } },
2498 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, { 1, 1, 1, 1 } },
2499 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, { 2, 1, 1, 1 } },
2500 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, { 1, 1, 1, 1 } },
2501 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, { 1, 1, 1, 1 } },
2502 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, { 1, 1, 1, 1 } },
2504 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, { 4, 1, 1, 1 } },
2505 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, { 3, 1, 1, 1 } },
2506 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, { 2, 1, 1, 1 } },
2507 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, { 1, 1, 1, 1 } },
2508 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, { 2, 1, 1, 1 } },
2509 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, { 1, 1, 1, 1 } },
2510 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, { 1, 1, 1, 1 } },
2511 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, { 1, 1, 1, 1 } },
2512 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, {26, 1, 1, 1 } },
2513 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, { 5, 1, 1, 1 } },
2515 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, { 2, 1, 1, 1 } },
2516 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, { 7, 1, 1, 1 } },
2517 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64, {15, 1, 1, 1 } },
2518 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32, {11, 1, 1, 1 } },
2519 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64, {31, 1, 1, 1 } },
2520 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, { 3, 1, 1, 1 } },
2521 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, { 7, 1, 1, 1 } },
2522 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, { 5, 1, 1, 1 } },
2523 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64, {15, 1, 1, 1 } },
2524 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, { 1, 1, 1, 1 } },
2525 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, { 3, 1, 1, 1 } },
2527 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, { 1, 1, 1, 1 } },
2528 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, { 3, 1, 1, 1 } },
2529 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, { 3, 1, 1, 1 } },
2530 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, { 1, 1, 1, 1 } },
2531 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, { 3, 1, 1, 1 } },
2532 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, { 3, 1, 1, 1 } },
2537 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, { 1, 1, 1, 1 } },
2538 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, { 1, 1, 1, 1 } },
2539 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, { 1, 1, 1, 1 } },
2540 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, { 1, 1, 1, 1 } },
2541 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, { 1, 1, 1, 1 } },
2542 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, { 1, 1, 1, 1 } },
2543 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, { 1, 1, 1, 1 } },
2544 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, { 1, 1, 1, 1 } },
2545 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, { 1, 1, 1, 1 } },
2546 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, { 1, 1, 1, 1 } },
2547 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, { 1, 1, 1, 1 } },
2548 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, { 1, 1, 1, 1 } },
2549 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, { 1, 1, 1, 1 } },
2550 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, { 1, 1, 1, 1 } },
2551 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, { 1, 1, 1, 1 } },
2552 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v64i1, { 1, 1, 1, 1 } },
2553 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1, { 1, 1, 1, 1 } },
2556 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, { 2, 1, 1, 1 } },
2557 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, { 2, 1, 1, 1 } },
2558 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, { 2, 1, 1, 1 } },
2559 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, { 2, 1, 1, 1 } },
2560 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, { 2, 1, 1, 1 } },
2561 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, { 2, 1, 1, 1 } },
2562 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, { 2, 1, 1, 1 } },
2563 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, { 2, 1, 1, 1 } },
2564 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, { 2, 1, 1, 1 } },
2565 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, { 2, 1, 1, 1 } },
2566 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, { 2, 1, 1, 1 } },
2567 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, { 2, 1, 1, 1 } },
2568 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, { 2, 1, 1, 1 } },
2569 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, { 2, 1, 1, 1 } },
2570 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, { 2, 1, 1, 1 } },
2571 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v64i1, { 2, 1, 1, 1 } },
2572 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1, { 2, 1, 1, 1 } },
2574 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 2, 1, 1, 1 } },
2575 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, { 2, 1, 1, 1 } },
2576 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 2, 1, 1, 1 } },
2577 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, { 2, 1, 1, 1 } },
2578 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 2, 1, 1, 1 } },
2579 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, { 2, 1, 1, 1 } },
2580 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, { 2, 1, 1, 1 } },
2581 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, { 2, 1, 1, 1 } },
2582 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, { 2, 1, 1, 1 } },
2583 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, { 2, 1, 1, 1 } },
2584 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, { 2, 1, 1, 1 } },
2585 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, { 2, 1, 1, 1 } },
2586 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, { 2, 1, 1, 1 } },
2587 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, { 2, 1, 1, 1 } },
2588 { ISD::TRUNCATE, MVT::v32i1, MVT::v16i16, { 2, 1, 1, 1 } },
2589 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i8, { 2, 1, 1, 1 } },
2590 { ISD::TRUNCATE, MVT::v64i1, MVT::v16i16, { 2, 1, 1, 1 } },
2592 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, { 2, 1, 1, 1 } },
2597 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, { 1, 1, 1, 1 } },
2598 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, { 1, 1, 1, 1 } },
2599 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, { 1, 1, 1, 1 } },
2600 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i1, { 1, 1, 1, 1 } },
2601 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 1, 1, 1, 1 } },
2602 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i1, { 1, 1, 1, 1 } },
2603 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, { 1, 1, 1, 1 } },
2604 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 1, 1, 1, 1 } },
2607 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, { 2, 1, 1, 1 } },
2608 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, { 2, 1, 1, 1 } },
2609 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, { 2, 1, 1, 1 } },
2610 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i1, { 2, 1, 1, 1 } },
2611 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 2, 1, 1, 1 } },
2612 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i1, { 2, 1, 1, 1 } },
2613 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, { 2, 1, 1, 1 } },
2614 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 2, 1, 1, 1 } },
2616 { ISD::TRUNCATE, MVT::v16i1, MVT::v4i64, { 2, 1, 1, 1 } },
2617 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, { 2, 1, 1, 1 } },
2618 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, { 2, 1, 1, 1 } },
2619 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, { 2, 1, 1, 1 } },
2620 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, { 2, 1, 1, 1 } },
2621 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, { 2, 1, 1, 1 } },
2622 { ISD::TRUNCATE, MVT::v8i1, MVT::v4i64, { 2, 1, 1, 1 } },
2623 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 2, 1, 1, 1 } },
2625 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, { 1, 1, 1, 1 } },
2626 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, { 1, 1, 1, 1 } },
2627 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, { 1, 1, 1, 1 } },
2628 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, { 1, 1, 1, 1 } },
2630 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, { 1, 1, 1, 1 } },
2631 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, { 1, 1, 1, 1 } },
2632 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, { 1, 1, 1, 1 } },
2633 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, { 1, 1, 1, 1 } },
2635 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, { 1, 1, 1, 1 } },
2636 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, { 1, 1, 1, 1 } },
2637 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, { 1, 1, 1, 1 } },
2638 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, { 1, 1, 1, 1 } },
2640 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, { 1, 1, 1, 1 } },
2641 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, { 1, 1, 1, 1 } },
2642 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, { 1, 1, 1, 1 } },
2643 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, { 1, 1, 1, 1 } },
2647 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2648 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2649 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, { 3, 1, 1, 1 } }, // sext+vpslld+vptestmd
2650 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, { 8, 1, 1, 1 } }, // split+2*v8i8
2651 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2652 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2653 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, { 3, 1, 1, 1 } }, // sext+vpsllq+vptestmq
2654 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, { 8, 1, 1, 1 } }, // split+2*v8i16
2655 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, { 2, 1, 1, 1 } }, // vpslld+vptestmd
2656 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, { 2, 1, 1, 1 } }, // vpslld+vptestmd
2657 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 2, 1, 1, 1 } }, // vpslld+vptestmd
2658 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, { 2, 1, 1, 1 } }, // vpslld+vptestmd
2659 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, { 2, 1, 1, 1 } }, // vpsllq+vptestmq
2660 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, { 2, 1, 1, 1 } }, // vpsllq+vptestmq
2661 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, { 1, 1, 1, 1 } }, // vpmovqd
2662 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, { 2, 1, 1, 1 } }, // vpmovqb
2663 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, { 2, 1, 1, 1 } }, // vpmovqw
2664 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, { 2, 1, 1, 1 } }, // vpmovwb
2668 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, { 5, 1, 1, 1 } },
2669 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, { 6, 1, 1, 1 } },
2670 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, { 5, 1, 1, 1 } },
2671 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, { 6, 1, 1, 1 } },
2672 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, { 5, 1, 1, 1 } },
2673 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, { 6, 1, 1, 1 } },
2674 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, {10, 1, 1, 1 } },
2675 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, {12, 1, 1, 1 } },
2679 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, { 4, 1, 1, 1 } },
2680 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, { 5, 1, 1, 1 } },
2681 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, { 4, 1, 1, 1 } },
2682 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, { 5, 1, 1, 1 } },
2683 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, { 4, 1, 1, 1 } },
2684 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, { 5, 1, 1, 1 } },
2685 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, {10, 1, 1, 1 } },
2686 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, {12, 1, 1, 1 } },
2688 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, { 1, 1, 1, 1 } }, // vpternlogd
2689 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, { 2, 1, 1, 1 } }, // vpternlogd+psrld
2690 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, { 1, 1, 1, 1 } }, // vpternlogd
2691 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, { 2, 1, 1, 1 } }, // vpternlogd+psrld
2692 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 1, 1, 1, 1 } }, // vpternlogd
2693 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 2, 1, 1, 1 } }, // vpternlogd+psrld
2694 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, { 1, 1, 1, 1 } }, // vpternlogd
2695 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, { 2, 1, 1, 1 } }, // vpternlogd+psrld
2697 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, { 1, 1, 1, 1 } }, // vpternlogq
2698 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, { 2, 1, 1, 1 } }, // vpternlogq+psrlq
2699 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 1, 1, 1, 1 } }, // vpternlogq
2700 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 2, 1, 1, 1 } }, // vpternlogq+psrlq
2702 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, { 1, 1, 1, 1 } },
2703 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, { 1, 1, 1, 1 } },
2704 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, { 1, 1, 1, 1 } },
2705 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, { 1, 1, 1, 1 } },
2706 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, { 1, 1, 1, 1 } },
2707 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, { 1, 1, 1, 1 } },
2708 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, { 1, 1, 1, 1 } },
2709 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, { 1, 1, 1, 1 } },
2710 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, { 1, 1, 1, 1 } },
2711 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, { 1, 1, 1, 1 } },
2712 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, { 1, 1, 1, 1 } },
2713 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, { 1, 1, 1, 1 } },
2715 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, { 1, 1, 1, 1 } },
2716 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, { 1, 1, 1, 1 } },
2717 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, { 1, 1, 1, 1 } },
2718 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, { 1, 1, 1, 1 } },
2720 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, { 1, 1, 1, 1 } },
2721 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, { 1, 1, 1, 1 } },
2722 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, { 1, 1, 1, 1 } },
2723 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, { 1, 1, 1, 1 } },
2724 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, { 1, 1, 1, 1 } },
2725 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, { 1, 1, 1, 1 } },
2726 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, { 1, 1, 1, 1 } },
2727 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, { 1, 1, 1, 1 } },
2728 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, { 1, 1, 1, 1 } },
2729 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, { 1, 1, 1, 1 } },
2730 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, { 5, 1, 1, 1 } },
2731 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, { 5, 1, 1, 1 } },
2732 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, { 5, 1, 1, 1 } },
2734 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, { 2, 1, 1, 1 } },
2735 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, { 2, 1, 1, 1 } },
2736 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, { 5, 1, 1, 1 } },
2738 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, { 1, 1, 1, 1 } },
2739 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, { 1, 1, 1, 1 } },
2740 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, { 1, 1, 1, 1 } },
2741 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, { 1, 1, 1, 1 } },
2742 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, { 1, 1, 1, 1 } },
2743 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, { 1, 1, 1, 1 } },
2744 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, { 1, 1, 1, 1 } },
2748 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 3, 1, 1, 1 } },
2749 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 3, 1, 1, 1 } },
2750 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 3, 1, 1, 1 } },
2751 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 3, 1, 1, 1 } },
2752 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, { 1, 1, 1, 1 } },
2753 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, { 1, 1, 1, 1 } },
2755 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, { 2, 1, 1, 1 } },
2756 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, { 2, 1, 1, 1 } },
2757 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, { 2, 1, 1, 1 } },
2758 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, { 2, 1, 1, 1 } },
2759 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, { 2, 1, 1, 1 } },
2760 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, { 2, 1, 1, 1 } },
2761 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, { 2, 1, 1, 1 } },
2762 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, { 2, 1, 1, 1 } },
2763 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, { 2, 1, 1, 1 } },
2764 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, { 2, 1, 1, 1 } },
2765 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, { 3, 1, 1, 1 } },
2766 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, { 3, 1, 1, 1 } },
2767 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, { 2, 1, 1, 1 } },
2768 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, { 2, 1, 1, 1 } },
2770 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 2, 1, 1, 1 } },
2772 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, { 4, 1, 1, 1 } },
2773 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, { 4, 1, 1, 1 } },
2774 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, { 1, 1, 1, 1 } },
2775 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, { 1, 1, 1, 1 } },
2776 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, { 1, 1, 1, 1 } },
2777 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, { 4, 1, 1, 1 } },
2778 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, { 4, 1, 1, 1 } },
2779 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, { 1, 1, 1, 1 } },
2780 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, { 1, 1, 1, 1 } },
2781 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, { 5, 1, 1, 1 } },
2782 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, { 1, 1, 1, 1 } },
2783 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, { 2, 1, 1, 1 } },
2785 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, { 3, 1, 1, 1 } },
2786 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, { 3, 1, 1, 1 } },
2788 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, { 1, 1, 1, 1 } },
2789 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, { 1, 1, 1, 1 } },
2790 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, { 1, 1, 1, 1 } },
2791 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, { 3, 1, 1, 1 } },
2793 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, { 3, 1, 1, 1 } },
2794 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, { 3, 1, 1, 1 } },
2795 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, { 1, 1, 1, 1 } },
2796 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, { 3, 1, 1, 1 } },
2797 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, { 4, 1, 1, 1 } },
2798 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, { 4, 1, 1, 1 } },
2799 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, { 3, 1, 1, 1 } },
2800 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, { 4, 1, 1, 1 } },
2802 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, { 2, 1, 1, 1 } },
2803 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, { 2, 1, 1, 1 } },
2804 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, { 2, 1, 1, 1 } },
2805 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, { 2, 1, 1, 1 } },
2806 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, { 1, 1, 1, 1 } },
2807 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, { 1, 1, 1, 1 } },
2808 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, { 3, 1, 1, 1 } },
2810 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, { 2, 1, 1, 1 } },
2811 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, { 2, 1, 1, 1 } },
2812 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, { 2, 1, 1, 1 } },
2813 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, { 2, 1, 1, 1 } },
2814 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, { 2, 1, 1, 1 } },
2815 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, { 1, 1, 1, 1 } },
2816 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, { 2, 1, 1, 1 } },
2817 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, { 2, 1, 1, 1 } },
2818 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, { 2, 1, 1, 1 } },
2819 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, { 4, 1, 1, 1 } },
2823 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, { 4, 1, 1, 1 } },
2824 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, { 4, 1, 1, 1 } },
2825 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, { 4, 1, 1, 1 } },
2826 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, { 4, 1, 1, 1 } },
2827 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, { 4, 1, 1, 1 } },
2828 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, { 4, 1, 1, 1 } },
2830 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, { 3, 1, 1, 1 } },
2831 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, { 3, 1, 1, 1 } },
2832 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, { 3, 1, 1, 1 } },
2833 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, { 3, 1, 1, 1 } },
2834 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, { 3, 1, 1, 1 } },
2835 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, { 3, 1, 1, 1 } },
2836 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, { 3, 1, 1, 1 } },
2837 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, { 3, 1, 1, 1 } },
2838 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, { 3, 1, 1, 1 } },
2839 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, { 3, 1, 1, 1 } },
2840 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, { 3, 1, 1, 1 } },
2841 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, { 3, 1, 1, 1 } },
2843 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, { 4, 1, 1, 1 } },
2844 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, { 5, 1, 1, 1 } },
2845 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, { 4, 1, 1, 1 } },
2846 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, { 9, 1, 1, 1 } },
2847 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, {11, 1, 1, 1 } },
2849 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, { 6, 1, 1, 1 } },
2850 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, { 6, 1, 1, 1 } },
2851 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, { 2, 1, 1, 1 } }, // and+extract+packuswb
2852 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, { 5, 1, 1, 1 } },
2853 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, { 5, 1, 1, 1 } },
2854 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, { 5, 1, 1, 1 } },
2855 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, { 3, 1, 1, 1 } }, // and+extract+2*packusdw
2856 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, { 2, 1, 1, 1 } },
2858 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, { 3, 1, 1, 1 } },
2859 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, { 3, 1, 1, 1 } },
2860 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, { 8, 1, 1, 1 } },
2861 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, { 4, 1, 1, 1 } },
2862 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, { 2, 1, 1, 1 } },
2863 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, { 4, 1, 1, 1 } },
2864 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, { 2, 1, 1, 1 } },
2865 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, { 2, 1, 1, 1 } },
2866 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, { 2, 1, 1, 1 } },
2867 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, { 4, 1, 1, 1 } },
2868 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, { 5, 1, 1, 1 } },
2869 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, { 8, 1, 1, 1 } },
2871 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, { 7, 1, 1, 1 } },
2872 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, { 7, 1, 1, 1 } },
2873 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, { 6, 1, 1, 1 } },
2874 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, { 4, 1, 1, 1 } },
2875 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, { 2, 1, 1, 1 } },
2876 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, { 4, 1, 1, 1 } },
2877 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, { 2, 1, 1, 1 } },
2878 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, { 4, 1, 1, 1 } },
2879 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, { 4, 1, 1, 1 } },
2880 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, { 5, 1, 1, 1 } },
2881 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, { 6, 1, 1, 1 } },
2882 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, { 8, 1, 1, 1 } },
2883 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, {10, 1, 1, 1 } },
2884 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, {10, 1, 1, 1 } },
2885 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, {18, 1, 1, 1 } },
2886 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, { 5, 1, 1, 1 } },
2887 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, {10, 1, 1, 1 } },
2889 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, { 2, 1, 1, 1 } },
2890 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, { 2, 1, 1, 1 } },
2891 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, { 2, 1, 1, 1 } },
2892 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, { 2, 1, 1, 1 } },
2893 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, { 2, 1, 1, 1 } },
2894 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, { 2, 1, 1, 1 } },
2895 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, { 2, 1, 1, 1 } },
2896 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, { 2, 1, 1, 1 } },
2897 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, { 2, 1, 1, 1 } },
2898 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, { 2, 1, 1, 1 } },
2899 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, { 5, 1, 1, 1 } },
2901 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, { 2, 1, 1, 1 } },
2902 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, { 2, 1, 1, 1 } },
2903 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, { 2, 1, 1, 1 } },
2904 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, { 2, 1, 1, 1 } },
2905 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, { 2, 1, 1, 1 } },
2906 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, { 2, 1, 1, 1 } },
2907 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, { 2, 1, 1, 1 } },
2908 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, { 2, 1, 1, 1 } },
2909 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, { 3, 1, 1, 1 } },
2910 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, { 4, 1, 1, 1 } },
2911 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, { 6, 1, 1, 1 } },
2912 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, { 7, 1, 1, 1 } },
2913 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, { 7, 1, 1, 1 } },
2915 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, { 1, 1, 1, 1 } },
2916 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, { 1, 1, 1, 1 } },
2920 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, { 1, 1, 1, 1 } },
2921 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, { 1, 1, 1, 1 } },
2922 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, { 1, 1, 1, 1 } },
2923 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, { 1, 1, 1, 1 } },
2924 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, { 1, 1, 1, 1 } },
2925 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, { 1, 1, 1, 1 } },
2926 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, { 1, 1, 1, 1 } },
2927 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, { 1, 1, 1, 1 } },
2928 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, { 1, 1, 1, 1 } },
2929 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, { 1, 1, 1, 1 } },
2930 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, { 1, 1, 1, 1 } },
2931 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, { 1, 1, 1, 1 } },
2934 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 1, 1, 1, 1 } }, // PMOVXZBQ
2935 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 1, 1, 1, 1 } }, // PMOVXZWQ
2936 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 1, 1, 1, 1 } }, // PMOVXZBD
2938 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, { 2, 1, 1, 1 } },
2939 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, { 2, 1, 1, 1 } },
2940 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, { 2, 1, 1, 1 } },
2942 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, { 1, 1, 1, 1 } },
2943 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, { 1, 1, 1, 1 } },
2944 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, { 1, 1, 1, 1 } },
2945 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, { 1, 1, 1, 1 } },
2946 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, { 1, 1, 1, 1 } },
2947 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, { 1, 1, 1, 1 } },
2948 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, { 1, 1, 1, 1 } },
2949 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, { 1, 1, 1, 1 } },
2950 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, { 1, 1, 1, 1 } },
2951 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, { 1, 1, 1, 1 } },
2952 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, { 2, 1, 1, 1 } },
2954 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, { 1, 1, 1, 1 } },
2955 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, { 1, 1, 1, 1 } },
2956 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, { 4, 1, 1, 1 } },
2957 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, { 4, 1, 1, 1 } },
2958 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, { 1, 1, 1, 1 } },
2959 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, { 1, 1, 1, 1 } },
2960 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, { 1, 1, 1, 1 } },
2961 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, { 1, 1, 1, 1 } },
2962 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, { 3, 1, 1, 1 } },
2963 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, { 3, 1, 1, 1 } },
2964 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, { 2, 1, 1, 1 } },
2965 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, {12, 1, 1, 1 } },
2966 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, {22, 1, 1, 1 } },
2967 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, { 4, 1, 1, 1 } },
2969 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, { 1, 1, 1, 1 } },
2970 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, { 1, 1, 1, 1 } },
2971 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, { 1, 1, 1, 1 } },
2972 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, { 1, 1, 1, 1 } },
2973 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, { 2, 1, 1, 1 } },
2974 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, { 2, 1, 1, 1 } },
2975 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, { 1, 1, 1, 1 } },
2976 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, { 1, 1, 1, 1 } },
2977 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, { 1, 1, 1, 1 } },
2978 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, { 1, 1, 1, 1 } },
2980 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, { 1, 1, 1, 1 } },
2981 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, { 4, 1, 1, 1 } },
2982 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, { 1, 1, 1, 1 } },
2983 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, { 4, 1, 1, 1 } },
2984 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, { 2, 1, 1, 1 } },
2985 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, { 2, 1, 1, 1 } },
2986 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, { 1, 1, 1, 1 } },
2987 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, { 1, 1, 1, 1 } },
2988 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, { 4, 1, 1, 1 } },
2989 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, { 4, 1, 1, 1 } },
2996 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, { 3, 1, 1, 1 } },
2997 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, { 3, 1, 1, 1 } },
2998 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, { 3, 1, 1, 1 } },
2999 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, { 3, 1, 1, 1 } },
3000 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, { 3, 1, 1, 1 } },
3001 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, { 4, 1, 1, 1 } },
3002 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, { 3, 1, 1, 1 } },
3003 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, { 4, 1, 1, 1 } },
3004 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, { 3, 1, 1, 1 } },
3005 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, { 4, 1, 1, 1 } },
3006 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, { 8, 1, 1, 1 } },
3007 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, { 8, 1, 1, 1 } },
3009 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, { 3, 1, 1, 1 } },
3010 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, { 3, 1, 1, 1 } },
3011 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, { 8, 1, 1, 1 } },
3012 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, { 9, 1, 1, 1 } },
3013 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, { 4, 1, 1, 1 } },
3014 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, { 4, 1, 1, 1 } },
3015 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, { 4, 1, 1, 1 } },
3016 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, { 4, 1, 1, 1 } },
3017 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, { 7, 1, 1, 1 } },
3018 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, { 7, 1, 1, 1 } },
3019 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, { 5, 1, 1, 1 } },
3020 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, {15, 1, 1, 1 } },
3021 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, {18, 1, 1, 1 } },
3023 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, { 4, 1, 1, 1 } },
3024 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, { 4, 1, 1, 1 } },
3025 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, { 4, 1, 1, 1 } },
3026 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, { 4, 1, 1, 1 } },
3027 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, { 6, 1, 1, 1 } },
3028 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, { 6, 1, 1, 1 } },
3029 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, { 5, 1, 1, 1 } },
3030 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, { 5, 1, 1, 1 } },
3031 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, { 4, 1, 1, 1 } },
3032 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, { 4, 1, 1, 1 } },
3034 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, { 4, 1, 1, 1 } },
3035 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, { 4, 1, 1, 1 } },
3036 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, { 4, 1, 1, 1 } },
3037 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, {15, 1, 1, 1 } },
3038 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, { 6, 1, 1, 1 } },
3039 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, { 6, 1, 1, 1 } },
3040 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, { 5, 1, 1, 1 } },
3041 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, { 5, 1, 1, 1 } },
3042 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, { 8, 1, 1, 1 } },
3043 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, { 8, 1, 1, 1 } },
3045 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, { 4, 1, 1, 1 } },
3046 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, { 4, 1, 1, 1 } },
3047 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, { 2, 1, 1, 1 } },
3048 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, { 3, 1, 1, 1 } },
3049 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, { 1, 1, 1, 1 } },
3050 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, { 2, 1, 1, 1 } },
3051 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, { 2, 1, 1, 1 } },
3052 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, { 3, 1, 1, 1 } },
3053 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, { 1, 1, 1, 1 } },
3054 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, { 2, 1, 1, 1 } },
3055 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, { 1, 1, 1, 1 } },
3056 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, { 2, 1, 1, 1 } },
3059 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, { 1, 1, 1, 1 } }, // PSHUFD
3060 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, { 2, 1, 1, 1 } }, // PUNPCKLWD+DQ
3061 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, { 3, 1, 1, 1 } }, // PUNPCKLBW+WD+PSHUFD
3062 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, { 1, 1, 1, 1 } }, // PUNPCKLWD
3063 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, { 2, 1, 1, 1 } }, // PUNPCKLBW+WD
3064 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, { 1, 1, 1, 1 } }, // PUNPCKLBW
3066 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, { 2, 1, 1, 1 } }, // PAND+PACKUSWB
3067 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, { 3, 1, 1, 1 } },
3068 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, { 3, 1, 1, 1 } }, // PAND+2*PACKUSWB
3069 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, { 7, 1, 1, 1 } },
3070 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, { 1, 1, 1, 1 } },
3071 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, { 3, 1, 1, 1 } },
3072 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, { 5, 1, 1, 1 } },
3073 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, {10, 1, 1, 1 } },
3074 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, { 4, 1, 1, 1 } }, // PAND+3*PACKUSWB
3075 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, { 2, 1, 1, 1 } }, // PSHUFD+PSHUFLW
3076 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, { 1, 1, 1, 1 } }, // PSHUFD
3080 { ISD::FP_ROUND, MVT::f16, MVT::f32, { 1, 1, 1, 1 } },
3081 { ISD::FP_ROUND, MVT::v8f16, MVT::v8f32, { 1, 1, 1, 1 } },
3082 { ISD::FP_ROUND, MVT::v4f16, MVT::v4f32, { 1, 1, 1, 1 } },
3083 { ISD::FP_EXTEND, MVT::f32, MVT::f16, { 1, 1, 1, 1 } },
3084 { ISD::FP_EXTEND, MVT::f64, MVT::f16, { 2, 1, 1, 1 } }, // vcvtph2ps+vcvtps2pd
3085 { ISD::FP_EXTEND, MVT::v8f32, MVT::v8f16, { 1, 1, 1, 1 } },
3086 { ISD::FP_EXTEND, MVT::v4f32, MVT::v4f16, { 1, 1, 1, 1 } },
3087 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f16, { 2, 1, 1, 1 } }, // vcvtph2ps+vcvtps2pd
3102 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
3108 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
3114 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
3121 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
3127 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy))
3132 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD,
3138 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
3145 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
3152 if (const auto *Entry = ConvertCostTableLookup(F16ConversionTbl, ISD,
3159 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
3166 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
3172 if ((ISD == ISD::FP_ROUND && SimpleDstTy == MVT::f16) ||
3173 (ISD == ISD::FP_EXTEND && SimpleSrcTy == MVT::f16)) {
3185 if (ISD == ISD::TRUNCATE && LTSrc.second == LTDest.second)
3191 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second))
3197 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second))
3203 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second))
3209 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD,
3215 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD,
3221 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD,
3227 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
3233 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
3239 if (const auto *Entry = ConvertCostTableLookup(F16ConversionTbl, ISD,
3246 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
3252 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
3259 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) &&
3263 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt;
3276 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) &&
3309 int ISD = TLI->InstructionOpcodeToISD(Opcode);
3310 assert(ISD && "Invalid opcode");
3387 { ISD::SETCC, MVT::v2i64, { 2, 5, 1, 2 } },
3389 { ISD::SELECT, MVT::v2f64, { 4, 4, 1, 3 } }, // vblendvpd
3390 { ISD::SELECT, MVT::v4f32, { 4, 4, 1, 3 } }, // vblendvps
3391 { ISD::SELECT, MVT::v2i64, { 4, 4, 1, 3 } }, // pblendvb
3392 { ISD::SELECT, MVT::v8i32, { 4, 4, 1, 3 } }, // pblendvb
3393 { ISD::SELECT, MVT::v8i16, { 4, 4, 1, 3 } }, // pblendvb
3394 { ISD::SELECT, MVT::v16i8, { 4, 4, 1, 3 } }, // pblendvb
3398 { ISD::SETCC, MVT::v32i16, { 1, 1, 1, 1 } },
3399 { ISD::SETCC, MVT::v16i16, { 1, 1, 1, 1 } },
3400 { ISD::SETCC, MVT::v64i8, { 1, 1, 1, 1 } },
3401 { ISD::SETCC, MVT::v32i8, { 1, 1, 1, 1 } },
3403 { ISD::SELECT, MVT::v32i16, { 1, 1, 1, 1 } },
3404 { ISD::SELECT, MVT::v64i8, { 1, 1, 1, 1 } },
3408 { ISD::SETCC, MVT::v8f64, { 1, 4, 1, 1 } },
3409 { ISD::SETCC, MVT::v4f64, { 1, 4, 1, 1 } },
3410 { ISD::SETCC, MVT::v16f32, { 1, 4, 1, 1 } },
3411 { ISD::SETCC, MVT::v8f32, { 1, 4, 1, 1 } },
3413 { ISD::SETCC, MVT::v8i64, { 1, 1, 1, 1 } },
3414 { ISD::SETCC, MVT::v4i64, { 1, 1, 1, 1 } },
3415 { ISD::SETCC, MVT::v2i64, { 1, 1, 1, 1 } },
3416 { ISD::SETCC, MVT::v16i32, { 1, 1, 1, 1 } },
3417 { ISD::SETCC, MVT::v8i32, { 1, 1, 1, 1 } },
3418 { ISD::SETCC, MVT::v32i16, { 3, 7, 5, 5 } },
3419 { ISD::SETCC, MVT::v64i8, { 3, 7, 5, 5 } },
3421 { ISD::SELECT, MVT::v8i64, { 1, 1, 1, 1 } },
3422 { ISD::SELECT, MVT::v4i64, { 1, 1, 1, 1 } },
3423 { ISD::SELECT, MVT::v2i64, { 1, 1, 1, 1 } },
3424 { ISD::SELECT, MVT::v16i32, { 1, 1, 1, 1 } },
3425 { ISD::SELECT, MVT::v8i32, { 1, 1, 1, 1 } },
3426 { ISD::SELECT, MVT::v4i32, { 1, 1, 1, 1 } },
3427 { ISD::SELECT, MVT::v8f64, { 1, 1, 1, 1 } },
3428 { ISD::SELECT, MVT::v4f64, { 1, 1, 1, 1 } },
3429 { ISD::SELECT, MVT::v2f64, { 1, 1, 1, 1 } },
3430 { ISD::SELECT, MVT::f64, { 1, 1, 1, 1 } },
3431 { ISD::SELECT, MVT::v16f32, { 1, 1, 1, 1 } },
3432 { ISD::SELECT, MVT::v8f32 , { 1, 1, 1, 1 } },
3433 { ISD::SELECT, MVT::v4f32, { 1, 1, 1, 1 } },
3434 { ISD::SELECT, MVT::f32 , { 1, 1, 1, 1 } },
3436 { ISD::SELECT, MVT::v32i16, { 2, 2, 4, 4 } },
3437 { ISD::SELECT, MVT::v16i16, { 1, 1, 1, 1 } },
3438 { ISD::SELECT, MVT::v8i16, { 1, 1, 1, 1 } },
3439 { ISD::SELECT, MVT::v64i8, { 2, 2, 4, 4 } },
3440 { ISD::SELECT, MVT::v32i8, { 1, 1, 1, 1 } },
3441 { ISD::SELECT, MVT::v16i8, { 1, 1, 1, 1 } },
3445 { ISD::SETCC, MVT::v4f64, { 1, 4, 1, 2 } },
3446 { ISD::SETCC, MVT::v2f64, { 1, 4, 1, 1 } },
3447 { ISD::SETCC, MVT::f64, { 1, 4, 1, 1 } },
3448 { ISD::SETCC, MVT::v8f32, { 1, 4, 1, 2 } },
3449 { ISD::SETCC, MVT::v4f32, { 1, 4, 1, 1 } },
3450 { ISD::SETCC, MVT::f32, { 1, 4, 1, 1 } },
3452 { ISD::SETCC, MVT::v4i64, { 1, 1, 1, 2 } },
3453 { ISD::SETCC, MVT::v8i32, { 1, 1, 1, 2 } },
3454 { ISD::SETCC, MVT::v16i16, { 1, 1, 1, 2 } },
3455 { ISD::SETCC, MVT::v32i8, { 1, 1, 1, 2 } },
3457 { ISD::SELECT, MVT::v4f64, { 2, 2, 1, 2 } }, // vblendvpd
3458 { ISD::SELECT, MVT::v8f32, { 2, 2, 1, 2 } }, // vblendvps
3459 { ISD::SELECT, MVT::v4i64, { 2, 2, 1, 2 } }, // pblendvb
3460 { ISD::SELECT, MVT::v8i32, { 2, 2, 1, 2 } }, // pblendvb
3461 { ISD::SELECT, MVT::v16i16, { 2, 2, 1, 2 } }, // pblendvb
3462 { ISD::SELECT, MVT::v32i8, { 2, 2, 1, 2 } }, // pblendvb
3466 { ISD::SETCC, MVT::v4i64, { 4, 2, 5, 6 } },
3467 { ISD::SETCC, MVT::v2i64, { 1, 1, 1, 1 } },
3471 { ISD::SETCC, MVT::v4f64, { 2, 3, 1, 2 } },
3472 { ISD::SETCC, MVT::v2f64, { 1, 3, 1, 1 } },
3473 { ISD::SETCC, MVT::f64, { 1, 3, 1, 1 } },
3474 { ISD::SETCC, MVT::v8f32, { 2, 3, 1, 2 } },
3475 { ISD::SETCC, MVT::v4f32, { 1, 3, 1, 1 } },
3476 { ISD::SETCC, MVT::f32, { 1, 3, 1, 1 } },
3479 { ISD::SETCC, MVT::v4i64, { 4, 2, 5, 6 } },
3480 { ISD::SETCC, MVT::v8i32, { 4, 2, 5, 6 } },
3481 { ISD::SETCC, MVT::v16i16, { 4, 2, 5, 6 } },
3482 { ISD::SETCC, MVT::v32i8, { 4, 2, 5, 6 } },
3484 { ISD::SELECT, MVT::v4f64, { 3, 3, 1, 2 } }, // vblendvpd
3485 { ISD::SELECT, MVT::v8f32, { 3, 3, 1, 2 } }, // vblendvps
3486 { ISD::SELECT, MVT::v4i64, { 3, 3, 1, 2 } }, // vblendvpd
3487 { ISD::SELECT, MVT::v8i32, { 3, 3, 1, 2 } }, // vblendvps
3488 { ISD::SELECT, MVT::v16i16, { 3, 3, 3, 3 } }, // vandps + vandnps + vorps
3489 { ISD::SELECT, MVT::v32i8, { 3, 3, 3, 3 } }, // vandps + vandnps + vorps
3493 { ISD::SETCC, MVT::v2i64, { 1, 2, 1, 2 } },
3497 { ISD::SETCC, MVT::v2f64, { 1, 5, 1, 1 } },
3498 { ISD::SETCC, MVT::v4f32, { 1, 5, 1, 1 } },
3500 { ISD::SELECT, MVT::v2f64, { 2, 2, 1, 2 } }, // blendvpd
3501 { ISD::SELECT, MVT::f64, { 2, 2, 1, 2 } }, // blendvpd
3502 { ISD::SELECT, MVT::v4f32, { 2, 2, 1, 2 } }, // blendvps
3503 { ISD::SELECT, MVT::f32 , { 2, 2, 1, 2 } }, // blendvps
3504 { ISD::SELECT, MVT::v2i64, { 2, 2, 1, 2 } }, // pblendvb
3505 { ISD::SELECT, MVT::v4i32, { 2, 2, 1, 2 } }, // pblendvb
3506 { ISD::SELECT, MVT::v8i16, { 2, 2, 1, 2 } }, // pblendvb
3507 { ISD::SELECT, MVT::v16i8, { 2, 2, 1, 2 } }, // pblendvb
3511 { ISD::SETCC, MVT::v2f64, { 2, 5, 1, 1 } },
3512 { ISD::SETCC, MVT::f64, { 1, 5, 1, 1 } },
3514 { ISD::SETCC, MVT::v2i64, { 5, 4, 5, 5 } }, // pcmpeqd/pcmpgtd expansion
3515 { ISD::SETCC, MVT::v4i32, { 1, 1, 1, 1 } },
3516 { ISD::SETCC, MVT::v8i16, { 1, 1, 1, 1 } },
3517 { ISD::SETCC, MVT::v16i8, { 1, 1, 1, 1 } },
3519 { ISD::SELECT, MVT::v2f64, { 2, 2, 3, 3 } }, // andpd + andnpd + orpd
3520 { ISD::SELECT, MVT::f64, { 2, 2, 3, 3 } }, // andpd + andnpd + orpd
3521 { ISD::SELECT, MVT::v2i64, { 2, 2, 3, 3 } }, // pand + pandn + por
3522 { ISD::SELECT, MVT::v4i32, { 2, 2, 3, 3 } }, // pand + pandn + por
3523 { ISD::SELECT, MVT::v8i16, { 2, 2, 3, 3 } }, // pand + pandn + por
3524 { ISD::SELECT, MVT::v16i8, { 2, 2, 3, 3 } }, // pand + pandn + por
3528 { ISD::SETCC, MVT::v4f32, { 2, 5, 1, 1 } },
3529 { ISD::SETCC, MVT::f32, { 1, 5, 1, 1 } },
3531 { ISD::SELECT, MVT::v4f32, { 2, 2, 3, 3 } }, // andps + andnps + orps
3532 { ISD::SELECT, MVT::f32, { 2, 2, 3, 3 } }, // andps + andnps + orps
3536 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
3541 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
3546 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
3551 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
3556 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
3561 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
3566 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
3571 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
3576 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
3581 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
3609 { ISD::FSHL, MVT::v8i64, { 1, 1, 1, 1 } },
3610 { ISD::FSHL, MVT::v4i64, { 1, 1, 1, 1 } },
3611 { ISD::FSHL, MVT::v2i64, { 1, 1, 1, 1 } },
3612 { ISD::FSHL, MVT::v16i32, { 1, 1, 1, 1 } },
3613 { ISD::FSHL, MVT::v8i32, { 1, 1, 1, 1 } },
3614 { ISD::FSHL, MVT::v4i32, { 1, 1, 1, 1 } },
3615 { ISD::FSHL, MVT::v32i16, { 1, 1, 1, 1 } },
3616 { ISD::FSHL, MVT::v16i16, { 1, 1, 1, 1 } },
3617 { ISD::FSHL, MVT::v8i16, { 1, 1, 1, 1 } },
3618 { ISD::ROTL, MVT::v32i16, { 1, 1, 1, 1 } },
3619 { ISD::ROTL, MVT::v16i16, { 1, 1, 1, 1 } },
3620 { ISD::ROTL, MVT::v8i16, { 1, 1, 1, 1 } },
3621 { ISD::ROTR, MVT::v32i16, { 1, 1, 1, 1 } },
3622 { ISD::ROTR, MVT::v16i16, { 1, 1, 1, 1 } },
3623 { ISD::ROTR, MVT::v8i16, { 1, 1, 1, 1 } },
3629 { ISD::CTPOP, MVT::v32i16, { 1, 1, 1, 1 } },
3630 { ISD::CTPOP, MVT::v64i8, { 1, 1, 1, 1 } },
3631 { ISD::CTPOP, MVT::v16i16, { 1, 1, 1, 1 } },
3632 { ISD::CTPOP, MVT::v32i8, { 1, 1, 1, 1 } },
3633 { ISD::CTPOP, MVT::v8i16, { 1, 1, 1, 1 } },
3634 { ISD::CTPOP, MVT::v16i8, { 1, 1, 1, 1 } },
3637 { ISD::CTPOP, MVT::v8i64, { 1, 1, 1, 1 } },
3638 { ISD::CTPOP, MVT::v16i32, { 1, 1, 1, 1 } },
3639 { ISD::CTPOP, MVT::v4i64, { 1, 1, 1, 1 } },
3640 { ISD::CTPOP, MVT::v8i32, { 1, 1, 1, 1 } },
3641 { ISD::CTPOP, MVT::v2i64, { 1, 1, 1, 1 } },
3642 { ISD::CTPOP, MVT::v4i32, { 1, 1, 1, 1 } },
3645 { ISD::CTLZ, MVT::v8i64, { 1, 5, 1, 1 } },
3646 { ISD::CTLZ, MVT::v16i32, { 1, 5, 1, 1 } },
3647 { ISD::CTLZ, MVT::v32i16, { 18, 27, 23, 27 } },
3648 { ISD::CTLZ, MVT::v64i8, { 3, 16, 9, 11 } },
3649 { ISD::CTLZ, MVT::v4i64, { 1, 5, 1, 1 } },
3650 { ISD::CTLZ, MVT::v8i32, { 1, 5, 1, 1 } },
3651 { ISD::CTLZ, MVT::v16i16, { 8, 19, 11, 13 } },
3652 { ISD::CTLZ, MVT::v32i8, { 2, 11, 9, 10 } },
3653 { ISD::CTLZ, MVT::v2i64, { 1, 5, 1, 1 } },
3654 { ISD::CTLZ, MVT::v4i32, { 1, 5, 1, 1 } },
3655 { ISD::CTLZ, MVT::v8i16, { 3, 15, 4, 6 } },
3656 { ISD::CTLZ, MVT::v16i8, { 2, 10, 9, 10 } },
3658 { ISD::CTTZ, MVT::v8i64, { 2, 8, 6, 7 } },
3659 { ISD::CTTZ, MVT::v16i32, { 2, 8, 6, 7 } },
3660 { ISD::CTTZ, MVT::v4i64, { 1, 8, 6, 6 } },
3661 { ISD::CTTZ, MVT::v8i32, { 1, 8, 6, 6 } },
3662 { ISD::CTTZ, MVT::v2i64, { 1, 8, 6, 6 } },
3663 { ISD::CTTZ, MVT::v4i32, { 1, 8, 6, 6 } },
3666 { ISD::ABS, MVT::v32i16, { 1, 1, 1, 1 } },
3667 { ISD::ABS, MVT::v64i8, { 1, 1, 1, 1 } },
3668 { ISD::BITREVERSE, MVT::v2i64, { 3, 10, 10, 11 } },
3669 { ISD::BITREVERSE, MVT::v4i64, { 3, 11, 10, 11 } },
3670 { ISD::BITREVERSE, MVT::v8i64, { 3, 12, 10, 14 } },
3671 { ISD::BITREVERSE, MVT::v4i32, { 3, 10, 10, 11 } },
3672 { ISD::BITREVERSE, MVT::v8i32, { 3, 11, 10, 11 } },
3673 { ISD::BITREVERSE, MVT::v16i32, { 3, 12, 10, 14 } },
3674 { ISD::BITREVERSE, MVT::v8i16, { 3, 10, 10, 11 } },
3675 { ISD::BITREVERSE, MVT::v16i16, { 3, 11, 10, 11 } },
3676 { ISD::BITREVERSE, MVT::v32i16, { 3, 12, 10, 14 } },
3677 { ISD::BITREVERSE, MVT::v16i8, { 2, 5, 9, 9 } },
3678 { ISD::BITREVERSE, MVT::v32i8, { 2, 5, 9, 9 } },
3679 { ISD::BITREVERSE, MVT::v64i8, { 2, 5, 9, 12 } },
3680 { ISD::BSWAP, MVT::v2i64, { 1, 1, 1, 2 } },
3681 { ISD::BSWAP, MVT::v4i64, { 1, 1, 1, 2 } },
3682 { ISD::BSWAP, MVT::v8i64, { 1, 1, 1, 2 } },
3683 { ISD::BSWAP, MVT::v4i32, { 1, 1, 1, 2 } },
3684 { ISD::BSWAP, MVT::v8i32, { 1, 1, 1, 2 } },
3685 { ISD::BSWAP, MVT::v16i32, { 1, 1, 1, 2 } },
3686 { ISD::BSWAP, MVT::v8i16, { 1, 1, 1, 2 } },
3687 { ISD::BSWAP, MVT::v16i16, { 1, 1, 1, 2 } },
3688 { ISD::BSWAP, MVT::v32i16, { 1, 1, 1, 2 } },
3689 { ISD::CTLZ, MVT::v8i64, { 8, 22, 23, 23 } },
3690 { ISD::CTLZ, MVT::v16i32, { 8, 23, 25, 25 } },
3691 { ISD::CTLZ, MVT::v32i16, { 4, 15, 15, 16 } },
3692 { ISD::CTLZ, MVT::v64i8, { 3, 12, 10, 9 } },
3693 { ISD::CTPOP, MVT::v2i64, { 3, 7, 10, 10 } },
3694 { ISD::CTPOP, MVT::v4i64, { 3, 7, 10, 10 } },
3695 { ISD::CTPOP, MVT::v8i64, { 3, 8, 10, 12 } },
3696 { ISD::CTPOP, MVT::v4i32, { 7, 11, 14, 14 } },
3697 { ISD::CTPOP, MVT::v8i32, { 7, 11, 14, 14 } },
3698 { ISD::CTPOP, MVT::v16i32, { 7, 12, 14, 16 } },
3699 { ISD::CTPOP, MVT::v8i16, { 2, 7, 11, 11 } },
3700 { ISD::CTPOP, MVT::v16i16, { 2, 7, 11, 11 } },
3701 { ISD::CTPOP, MVT::v32i16, { 3, 7, 11, 13 } },
3702 { ISD::CTPOP, MVT::v16i8, { 2, 4, 8, 8 } },
3703 { ISD::CTPOP, MVT::v32i8, { 2, 4, 8, 8 } },
3704 { ISD::CTPOP, MVT::v64i8, { 2, 5, 8, 10 } },
3705 { ISD::CTTZ, MVT::v8i16, { 3, 9, 14, 14 } },
3706 { ISD::CTTZ, MVT::v16i16, { 3, 9, 14, 14 } },
3707 { ISD::CTTZ, MVT::v32i16, { 3, 10, 14, 16 } },
3708 { ISD::CTTZ, MVT::v16i8, { 2, 6, 11, 11 } },
3709 { ISD::CTTZ, MVT::v32i8, { 2, 6, 11, 11 } },
3710 { ISD::CTTZ, MVT::v64i8, { 3, 7, 11, 13 } },
3711 { ISD::ROTL, MVT::v32i16, { 2, 8, 6, 8 } },
3712 { ISD::ROTL, MVT::v16i16, { 2, 8, 6, 7 } },
3713 { ISD::ROTL, MVT::v8i16, { 2, 7, 6, 7 } },
3714 { ISD::ROTL, MVT::v64i8, { 5, 6, 11, 12 } },
3715 { ISD::ROTL, MVT::v32i8, { 5, 15, 7, 10 } },
3716 { ISD::ROTL, MVT::v16i8, { 5, 15, 7, 10 } },
3717 { ISD::ROTR, MVT::v32i16, { 2, 8, 6, 8 } },
3718 { ISD::ROTR, MVT::v16i16, { 2, 8, 6, 7 } },
3719 { ISD::ROTR, MVT::v8i16, { 2, 7, 6, 7 } },
3720 { ISD::ROTR, MVT::v64i8, { 5, 6, 12, 14 } },
3721 { ISD::ROTR, MVT::v32i8, { 5, 14, 6, 9 } },
3722 { ISD::ROTR, MVT::v16i8, { 5, 14, 6, 9 } },
3729 { ISD::SADDSAT, MVT::v32i16, { 1, 1, 1, 1 } },
3730 { ISD::SADDSAT, MVT::v64i8, { 1, 1, 1, 1 } },
3731 { ISD::SMAX, MVT::v32i16, { 1, 1, 1, 1 } },
3732 { ISD::SMAX, MVT::v64i8, { 1, 1, 1, 1 } },
3733 { ISD::SMIN, MVT::v32i16, { 1, 1, 1, 1 } },
3734 { ISD::SMIN, MVT::v64i8, { 1, 1, 1, 1 } },
3735 { ISD::SMULO, MVT::v32i16, { 3, 6, 4, 4 } },
3736 { ISD::SMULO, MVT::v64i8, { 8, 21, 17, 18 } },
3737 { ISD::UMULO, MVT::v32i16, { 2, 5, 3, 3 } },
3738 { ISD::UMULO, MVT::v64i8, { 8, 15, 15, 16 } },
3739 { ISD::SSUBSAT, MVT::v32i16, { 1, 1, 1, 1 } },
3740 { ISD::SSUBSAT, MVT::v64i8, { 1, 1, 1, 1 } },
3741 { ISD::UADDSAT, MVT::v32i16, { 1, 1, 1, 1 } },
3742 { ISD::UADDSAT, MVT::v64i8, { 1, 1, 1, 1 } },
3743 { ISD::UMAX, MVT::v32i16, { 1, 1, 1, 1 } },
3744 { ISD::UMAX, MVT::v64i8, { 1, 1, 1, 1 } },
3745 { ISD::UMIN, MVT::v32i16, { 1, 1, 1, 1 } },
3746 { ISD::UMIN, MVT::v64i8, { 1, 1, 1, 1 } },
3747 { ISD::USUBSAT, MVT::v32i16, { 1, 1, 1, 1 } },
3748 { ISD::USUBSAT, MVT::v64i8, { 1, 1, 1, 1 } },
3751 { ISD::ABS, MVT::v8i64, { 1, 1, 1, 1 } },
3752 { ISD::ABS, MVT::v4i64, { 1, 1, 1, 1 } },
3753 { ISD::ABS, MVT::v2i64, { 1, 1, 1, 1 } },
3754 { ISD::ABS, MVT::v16i32, { 1, 1, 1, 1 } },
3755 { ISD::ABS, MVT::v8i32, { 1, 1, 1, 1 } },
3756 { ISD::ABS, MVT::v32i16, { 2, 7, 4, 4 } },
3757 { ISD::ABS, MVT::v16i16, { 1, 1, 1, 1 } },
3758 { ISD::ABS, MVT::v64i8, { 2, 7, 4, 4 } },
3759 { ISD::ABS, MVT::v32i8, { 1, 1, 1, 1 } },
3760 { ISD::BITREVERSE, MVT::v8i64, { 9, 13, 20, 20 } },
3761 { ISD::BITREVERSE, MVT::v16i32, { 9, 13, 20, 20 } },
3762 { ISD::BITREVERSE, MVT::v32i16, { 9, 13, 20, 20 } },
3763 { ISD::BITREVERSE, MVT::v64i8, { 6, 11, 17, 17 } },
3764 { ISD::BSWAP, MVT::v8i64, { 4, 7, 5, 5 } },
3765 { ISD::BSWAP, MVT::v16i32, { 4, 7, 5, 5 } },
3766 { ISD::BSWAP, MVT::v32i16, { 4, 7, 5, 5 } },
3767 { ISD::CTLZ, MVT::v8i64, { 10, 28, 32, 32 } },
3768 { ISD::CTLZ, MVT::v16i32, { 12, 30, 38, 38 } },
3769 { ISD::CTLZ, MVT::v32i16, { 8, 15, 29, 29 } },
3770 { ISD::CTLZ, MVT::v64i8, { 6, 11, 19, 19 } },
3771 { ISD::CTPOP, MVT::v8i64, { 16, 16, 19, 19 } },
3772 { ISD::CTPOP, MVT::v16i32, { 24, 19, 27, 27 } },
3773 { ISD::CTPOP, MVT::v32i16, { 18, 15, 22, 22 } },
3774 { ISD::CTPOP, MVT::v64i8, { 12, 11, 16, 16 } },
3775 { ISD::CTTZ, MVT::v8i64, { 2, 8, 6, 7 } },
3776 { ISD::CTTZ, MVT::v16i32, { 2, 8, 6, 7 } },
3777 { ISD::CTTZ, MVT::v32i16, { 7, 17, 27, 27 } },
3778 { ISD::CTTZ, MVT::v64i8, { 6, 13, 21, 21 } },
3779 { ISD::ROTL, MVT::v8i64, { 1, 1, 1, 1 } },
3780 { ISD::ROTL, MVT::v4i64, { 1, 1, 1, 1 } },
3781 { ISD::ROTL, MVT::v2i64, { 1, 1, 1, 1 } },
3782 { ISD::ROTL, MVT::v16i32, { 1, 1, 1, 1 } },
3783 { ISD::ROTL, MVT::v8i32, { 1, 1, 1, 1 } },
3784 { ISD::ROTL, MVT::v4i32, { 1, 1, 1, 1 } },
3785 { ISD::ROTR, MVT::v8i64, { 1, 1, 1, 1 } },
3786 { ISD::ROTR, MVT::v4i64, { 1, 1, 1, 1 } },
3787 { ISD::ROTR, MVT::v2i64, { 1, 1, 1, 1 } },
3788 { ISD::ROTR, MVT::v16i32, { 1, 1, 1, 1 } },
3789 { ISD::ROTR, MVT::v8i32, { 1, 1, 1, 1 } },
3790 { ISD::ROTR, MVT::v4i32, { 1, 1, 1, 1 } },
3797 { ISD::SADDSAT, MVT::v2i64, { 3, 3, 8, 9 } },
3798 { ISD::SADDSAT, MVT::v4i64, { 2, 2, 6, 7 } },
3799 { ISD::SADDSAT, MVT::v8i64, { 3, 3, 6, 7 } },
3800 { ISD::SADDSAT, MVT::v4i32, { 2, 2, 6, 7 } },
3801 { ISD::SADDSAT, MVT::v8i32, { 2, 2, 6, 7 } },
3802 { ISD::SADDSAT, MVT::v16i32, { 3, 3, 6, 7 } },
3803 { ISD::SADDSAT, MVT::v32i16, { 2, 2, 2, 2 } },
3804 { ISD::SADDSAT, MVT::v64i8, { 2, 2, 2, 2 } },
3805 { ISD::SMAX, MVT::v8i64, { 1, 3, 1, 1 } },
3806 { ISD::SMAX, MVT::v16i32, { 1, 1, 1, 1 } },
3807 { ISD::SMAX, MVT::v32i16, { 3, 7, 5, 5 } },
3808 { ISD::SMAX, MVT::v64i8, { 3, 7, 5, 5 } },
3809 { ISD::SMAX, MVT::v4i64, { 1, 3, 1, 1 } },
3810 { ISD::SMAX, MVT::v2i64, { 1, 3, 1, 1 } },
3811 { ISD::SMIN, MVT::v8i64, { 1, 3, 1, 1 } },
3812 { ISD::SMIN, MVT::v16i32, { 1, 1, 1, 1 } },
3813 { ISD::SMIN, MVT::v32i16, { 3, 7, 5, 5 } },
3814 { ISD::SMIN, MVT::v64i8, { 3, 7, 5, 5 } },
3815 { ISD::SMIN, MVT::v4i64, { 1, 3, 1, 1 } },
3816 { ISD::SMIN, MVT::v2i64, { 1, 3, 1, 1 } },
3817 { ISD::SMULO, MVT::v8i64, { 44, 44, 81, 93 } },
3818 { ISD::SMULO, MVT::v16i32, { 5, 12, 9, 11 } },
3819 { ISD::SMULO, MVT::v32i16, { 6, 12, 17, 17 } },
3820 { ISD::SMULO, MVT::v64i8, { 22, 28, 42, 42 } },
3821 { ISD::SSUBSAT, MVT::v2i64, { 2, 13, 9, 10 } },
3822 { ISD::SSUBSAT, MVT::v4i64, { 2, 15, 7, 8 } },
3823 { ISD::SSUBSAT, MVT::v8i64, { 2, 14, 7, 8 } },
3824 { ISD::SSUBSAT, MVT::v4i32, { 2, 14, 7, 8 } },
3825 { ISD::SSUBSAT, MVT::v8i32, { 2, 15, 7, 8 } },
3826 { ISD::SSUBSAT, MVT::v16i32, { 2, 14, 7, 8 } },
3827 { ISD::SSUBSAT, MVT::v32i16, { 2, 2, 2, 2 } },
3828 { ISD::SSUBSAT, MVT::v64i8, { 2, 2, 2, 2 } },
3829 { ISD::UMAX, MVT::v8i64, { 1, 3, 1, 1 } },
3830 { ISD::UMAX, MVT::v16i32, { 1, 1, 1, 1 } },
3831 { ISD::UMAX, MVT::v32i16, { 3, 7, 5, 5 } },
3832 { ISD::UMAX, MVT::v64i8, { 3, 7, 5, 5 } },
3833 { ISD::UMAX, MVT::v4i64, { 1, 3, 1, 1 } },
3834 { ISD::UMAX, MVT::v2i64, { 1, 3, 1, 1 } },
3835 { ISD::UMIN, MVT::v8i64, { 1, 3, 1, 1 } },
3836 { ISD::UMIN, MVT::v16i32, { 1, 1, 1, 1 } },
3837 { ISD::UMIN, MVT::v32i16, { 3, 7, 5, 5 } },
3838 { ISD::UMIN, MVT::v64i8, { 3, 7, 5, 5 } },
3839 { ISD::UMIN, MVT::v4i64, { 1, 3, 1, 1 } },
3840 { ISD::UMIN, MVT::v2i64, { 1, 3, 1, 1 } },
3841 { ISD::UMULO, MVT::v8i64, { 52, 52, 95, 104} },
3842 { ISD::UMULO, MVT::v16i32, { 5, 12, 8, 10 } },
3843 { ISD::UMULO, MVT::v32i16, { 5, 13, 16, 16 } },
3844 { ISD::UMULO, MVT::v64i8, { 18, 24, 30, 30 } },
3845 { ISD::UADDSAT, MVT::v2i64, { 1, 4, 4, 4 } },
3846 { ISD::UADDSAT, MVT::v4i64, { 1, 4, 4, 4 } },
3847 { ISD::UADDSAT, MVT::v8i64, { 1, 4, 4, 4 } },
3848 { ISD::UADDSAT, MVT::v4i32, { 1, 2, 4, 4 } },
3849 { ISD::UADDSAT, MVT::v8i32, { 1, 2, 4, 4 } },
3850 { ISD::UADDSAT, MVT::v16i32, { 2, 2, 4, 4 } },
3851 { ISD::UADDSAT, MVT::v32i16, { 2, 2, 2, 2 } },
3852 { ISD::UADDSAT, MVT::v64i8, { 2, 2, 2, 2 } },
3853 { ISD::USUBSAT, MVT::v2i64, { 1, 4, 2, 2 } },
3854 { ISD::USUBSAT, MVT::v4i64, { 1, 4, 2, 2 } },
3855 { ISD::USUBSAT, MVT::v8i64, { 1, 4, 2, 2 } },
3856 { ISD::USUBSAT, MVT::v8i32, { 1, 2, 2, 2 } },
3857 { ISD::USUBSAT, MVT::v16i32, { 1, 2, 2, 2 } },
3858 { ISD::USUBSAT, MVT::v32i16, { 2, 2, 2, 2 } },
3859 { ISD::USUBSAT, MVT::v64i8, { 2, 2, 2, 2 } },
3860 { ISD::FMAXNUM, MVT::f32, { 2, 2, 3, 3 } },
3861 { ISD::FMAXNUM, MVT::v4f32, { 1, 1, 3, 3 } },
3862 { ISD::FMAXNUM, MVT::v8f32, { 2, 2, 3, 3 } },
3863 { ISD::FMAXNUM, MVT::v16f32, { 4, 4, 3, 3 } },
3864 { ISD::FMAXNUM, MVT::f64, { 2, 2, 3, 3 } },
3865 { ISD::FMAXNUM, MVT::v2f64, { 1, 1, 3, 3 } },
3866 { ISD::FMAXNUM, MVT::v4f64, { 2, 2, 3, 3 } },
3867 { ISD::FMAXNUM, MVT::v8f64, { 3, 3, 3, 3 } },
3868 { ISD::FSQRT, MVT::f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/
3869 { ISD::FSQRT, MVT::v4f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/
3870 { ISD::FSQRT, MVT::v8f32, { 6, 12, 1, 1 } }, // Skylake from http://www.agner.org/
3871 { ISD::FSQRT, MVT::v16f32, { 12, 20, 1, 3 } }, // Skylake from http://www.agner.org/
3872 { ISD::FSQRT, MVT::f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/
3873 { ISD::FSQRT, MVT::v2f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/
3874 { ISD::FSQRT, MVT::v4f64, { 12, 18, 1, 1 } }, // Skylake from http://www.agner.org/
3875 { ISD::FSQRT, MVT::v8f64, { 24, 32, 1, 3 } }, // Skylake from http://www.agner.org/
3878 { ISD::BITREVERSE, MVT::v4i64, { 3, 6, 5, 6 } },
3879 { ISD::BITREVERSE, MVT::v8i32, { 3, 6, 5, 6 } },
3880 { ISD::BITREVERSE, MVT::v16i16, { 3, 6, 5, 6 } },
3881 { ISD::BITREVERSE, MVT::v32i8, { 3, 6, 5, 6 } },
3882 { ISD::BITREVERSE, MVT::v2i64, { 2, 7, 1, 1 } },
3883 { ISD::BITREVERSE, MVT::v4i32, { 2, 7, 1, 1 } },
3884 { ISD::BITREVERSE, MVT::v8i16, { 2, 7, 1, 1 } },
3885 { ISD::BITREVERSE, MVT::v16i8, { 2, 7, 1, 1 } },
3886 { ISD::BITREVERSE, MVT::i64, { 2, 2, 3, 4 } },
3887 { ISD::BITREVERSE, MVT::i32, { 2, 2, 3, 4 } },
3888 { ISD::BITREVERSE, MVT::i16, { 2, 2, 3, 4 } },
3889 { ISD::BITREVERSE, MVT::i8, { 2, 2, 3, 4 } },
3891 { ISD::ROTL, MVT::v4i64, { 4, 7, 5, 6 } },
3892 { ISD::ROTL, MVT::v8i32, { 4, 7, 5, 6 } },
3893 { ISD::ROTL, MVT::v16i16, { 4, 7, 5, 6 } },
3894 { ISD::ROTL, MVT::v32i8, { 4, 7, 5, 6 } },
3895 { ISD::ROTL, MVT::v2i64, { 1, 3, 1, 1 } },
3896 { ISD::ROTL, MVT::v4i32, { 1, 3, 1, 1 } },
3897 { ISD::ROTL, MVT::v8i16, { 1, 3, 1, 1 } },
3898 { ISD::ROTL, MVT::v16i8, { 1, 3, 1, 1 } },
3899 { ISD::ROTR, MVT::v4i64, { 4, 7, 8, 9 } },
3900 { ISD::ROTR, MVT::v8i32, { 4, 7, 8, 9 } },
3901 { ISD::ROTR, MVT::v16i16, { 4, 7, 8, 9 } },
3902 { ISD::ROTR, MVT::v32i8, { 4, 7, 8, 9 } },
3903 { ISD::ROTR, MVT::v2i64, { 1, 3, 3, 3 } },
3904 { ISD::ROTR, MVT::v4i32, { 1, 3, 3, 3 } },
3905 { ISD::ROTR, MVT::v8i16, { 1, 3, 3, 3 } },
3906 { ISD::ROTR, MVT::v16i8, { 1, 3, 3, 3 } },
3917 { ISD::ABS, MVT::v2i64, { 2, 4, 3, 5 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
3918 { ISD::ABS, MVT::v4i64, { 2, 4, 3, 5 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
3919 { ISD::ABS, MVT::v4i32, { 1, 1, 1, 1 } },
3920 { ISD::ABS, MVT::v8i32, { 1, 1, 1, 2 } },
3921 { ISD::ABS, MVT::v8i16, { 1, 1, 1, 1 } },
3922 { ISD::ABS, MVT::v16i16, { 1, 1, 1, 2 } },
3923 { ISD::ABS, MVT::v16i8, { 1, 1, 1, 1 } },
3924 { ISD::ABS, MVT::v32i8, { 1, 1, 1, 2 } },
3925 { ISD::BITREVERSE, MVT::v2i64, { 3, 11, 10, 11 } },
3926 { ISD::BITREVERSE, MVT::v4i64, { 5, 11, 10, 17 } },
3927 { ISD::BITREVERSE, MVT::v4i32, { 3, 11, 10, 11 } },
3928 { ISD::BITREVERSE, MVT::v8i32, { 5, 11, 10, 17 } },
3929 { ISD::BITREVERSE, MVT::v8i16, { 3, 11, 10, 11 } },
3930 { ISD::BITREVERSE, MVT::v16i16, { 5, 11, 10, 17 } },
3931 { ISD::BITREVERSE, MVT::v16i8, { 3, 6, 9, 9 } },
3932 { ISD::BITREVERSE, MVT::v32i8, { 4, 5, 9, 15 } },
3933 { ISD::BSWAP, MVT::v2i64, { 1, 2, 1, 2 } },
3934 { ISD::BSWAP, MVT::v4i64, { 1, 3, 1, 2 } },
3935 { ISD::BSWAP, MVT::v4i32, { 1, 2, 1, 2 } },
3936 { ISD::BSWAP, MVT::v8i32, { 1, 3, 1, 2 } },
3937 { ISD::BSWAP, MVT::v8i16, { 1, 2, 1, 2 } },
3938 { ISD::BSWAP, MVT::v16i16, { 1, 3, 1, 2 } },
3939 { ISD::CTLZ, MVT::v2i64, { 7, 18, 24, 25 } },
3940 { ISD::CTLZ, MVT::v4i64, { 14, 18, 24, 44 } },
3941 { ISD::CTLZ, MVT::v4i32, { 5, 16, 19, 20 } },
3942 { ISD::CTLZ, MVT::v8i32, { 10, 16, 19, 34 } },
3943 { ISD::CTLZ, MVT::v8i16, { 4, 13, 14, 15 } },
3944 { ISD::CTLZ, MVT::v16i16, { 6, 14, 14, 24 } },
3945 { ISD::CTLZ, MVT::v16i8, { 3, 12, 9, 10 } },
3946 { ISD::CTLZ, MVT::v32i8, { 4, 12, 9, 14 } },
3947 { ISD::CTPOP, MVT::v2i64, { 3, 9, 10, 10 } },
3948 { ISD::CTPOP, MVT::v4i64, { 4, 9, 10, 14 } },
3949 { ISD::CTPOP, MVT::v4i32, { 7, 12, 14, 14 } },
3950 { ISD::CTPOP, MVT::v8i32, { 7, 12, 14, 18 } },
3951 { ISD::CTPOP, MVT::v8i16, { 3, 7, 11, 11 } },
3952 { ISD::CTPOP, MVT::v16i16, { 6, 8, 11, 18 } },
3953 { ISD::CTPOP, MVT::v16i8, { 2, 5, 8, 8 } },
3954 { ISD::CTPOP, MVT::v32i8, { 3, 5, 8, 12 } },
3955 { ISD::CTTZ, MVT::v2i64, { 4, 11, 13, 13 } },
3956 { ISD::CTTZ, MVT::v4i64, { 5, 11, 13, 20 } },
3957 { ISD::CTTZ, MVT::v4i32, { 7, 14, 17, 17 } },
3958 { ISD::CTTZ, MVT::v8i32, { 7, 15, 17, 24 } },
3959 { ISD::CTTZ, MVT::v8i16, { 4, 9, 14, 14 } },
3960 { ISD::CTTZ, MVT::v16i16, { 6, 9, 14, 24 } },
3961 { ISD::CTTZ, MVT::v16i8, { 3, 7, 11, 11 } },
3962 { ISD::CTTZ, MVT::v32i8, { 5, 7, 11, 18 } },
3963 { ISD::SADDSAT, MVT::v2i64, { 4, 13, 8, 11 } },
3964 { ISD::SADDSAT, MVT::v4i64, { 3, 10, 8, 12 } },
3965 { ISD::SADDSAT, MVT::v4i32, { 2, 6, 7, 9 } },
3966 { ISD::SADDSAT, MVT::v8i32, { 4, 6, 7, 13 } },
3967 { ISD::SADDSAT, MVT::v16i16, { 1, 1, 1, 2 } },
3968 { ISD::SADDSAT, MVT::v32i8, { 1, 1, 1, 2 } },
3969 { ISD::SMAX, MVT::v2i64, { 2, 7, 2, 3 } },
3970 { ISD::SMAX, MVT::v4i64, { 2, 7, 2, 3 } },
3971 { ISD::SMAX, MVT::v8i32, { 1, 1, 1, 2 } },
3972 { ISD::SMAX, MVT::v16i16, { 1, 1, 1, 2 } },
3973 { ISD::SMAX, MVT::v32i8, { 1, 1, 1, 2 } },
3974 { ISD::SMIN, MVT::v2i64, { 2, 7, 2, 3 } },
3975 { ISD::SMIN, MVT::v4i64, { 2, 7, 2, 3 } },
3976 { ISD::SMIN, MVT::v8i32, { 1, 1, 1, 2 } },
3977 { ISD::SMIN, MVT::v16i16, { 1, 1, 1, 2 } },
3978 { ISD::SMIN, MVT::v32i8, { 1, 1, 1, 2 } },
3979 { ISD::SMULO, MVT::v4i64, { 20, 20, 33, 37 } },
3980 { ISD::SMULO, MVT::v2i64, { 8, 8, 13, 15 } },
3981 { ISD::SMULO, MVT::v8i32, { 8, 20, 13, 24 } },
3982 { ISD::SMULO, MVT::v4i32, { 5, 15, 11, 12 } },
3983 { ISD::SMULO, MVT::v16i16, { 4, 14, 8, 14 } },
3984 { ISD::SMULO, MVT::v8i16, { 3, 9, 6, 6 } },
3985 { ISD::SMULO, MVT::v32i8, { 9, 15, 18, 35 } },
3986 { ISD::SMULO, MVT::v16i8, { 6, 22, 14, 21 } },
3987 { ISD::SSUBSAT, MVT::v2i64, { 4, 13, 9, 13 } },
3988 { ISD::SSUBSAT, MVT::v4i64, { 4, 15, 9, 13 } },
3989 { ISD::SSUBSAT, MVT::v4i32, { 3, 14, 9, 11 } },
3990 { ISD::SSUBSAT, MVT::v8i32, { 4, 15, 9, 16 } },
3991 { ISD::SSUBSAT, MVT::v16i16, { 1, 1, 1, 2 } },
3992 { ISD::SSUBSAT, MVT::v32i8, { 1, 1, 1, 2 } },
3993 { ISD::UADDSAT, MVT::v2i64, { 2, 8, 6, 6 } },
3994 { ISD::UADDSAT, MVT::v4i64, { 3, 8, 6, 10 } },
3995 { ISD::UADDSAT, MVT::v8i32, { 2, 2, 4, 8 } },
3996 { ISD::UADDSAT, MVT::v16i16, { 1, 1, 1, 2 } },
3997 { ISD::UADDSAT, MVT::v32i8, { 1, 1, 1, 2 } },
3998 { ISD::UMAX, MVT::v2i64, { 2, 8, 5, 6 } },
3999 { ISD::UMAX, MVT::v4i64, { 2, 8, 5, 8 } },
4000 { ISD::UMAX, MVT::v8i32, { 1, 1, 1, 2 } },
4001 { ISD::UMAX, MVT::v16i16, { 1, 1, 1, 2 } },
4002 { ISD::UMAX, MVT::v32i8, { 1, 1, 1, 2 } },
4003 { ISD::UMIN, MVT::v2i64, { 2, 8, 5, 6 } },
4004 { ISD::UMIN, MVT::v4i64, { 2, 8, 5, 8 } },
4005 { ISD::UMIN, MVT::v8i32, { 1, 1, 1, 2 } },
4006 { ISD::UMIN, MVT::v16i16, { 1, 1, 1, 2 } },
4007 { ISD::UMIN, MVT::v32i8, { 1, 1, 1, 2 } },
4008 { ISD::UMULO, MVT::v4i64, { 24, 24, 39, 43 } },
4009 { ISD::UMULO, MVT::v2i64, { 10, 10, 15, 19 } },
4010 { ISD::UMULO, MVT::v8i32, { 8, 11, 13, 23 } },
4011 { ISD::UMULO, MVT::v4i32, { 5, 12, 11, 12 } },
4012 { ISD::UMULO, MVT::v16i16, { 4, 6, 8, 13 } },
4013 { ISD::UMULO, MVT::v8i16, { 2, 8, 6, 6 } },
4014 { ISD::UMULO, MVT::v32i8, { 9, 13, 17, 33 } },
4015 { ISD::UMULO, MVT::v16i8, { 6, 19, 13, 20 } },
4016 { ISD::USUBSAT, MVT::v2i64, { 2, 7, 6, 6 } },
4017 { ISD::USUBSAT, MVT::v4i64, { 3, 7, 6, 10 } },
4018 { ISD::USUBSAT, MVT::v8i32, { 2, 2, 2, 4 } },
4019 { ISD::USUBSAT, MVT::v16i16, { 1, 1, 1, 2 } },
4020 { ISD::USUBSAT, MVT::v32i8, { 1, 1, 1, 2 } },
4021 { ISD::FMAXNUM, MVT::f32, { 2, 7, 3, 5 } }, // MAXSS + CMPUNORDSS + BLENDVPS
4022 { ISD::FMAXNUM, MVT::v4f32, { 2, 7, 3, 5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
4023 { ISD::FMAXNUM, MVT::v8f32, { 3, 7, 3, 6 } }, // MAXPS + CMPUNORDPS + BLENDVPS
4024 { ISD::FMAXNUM, MVT::f64, { 2, 7, 3, 5 } }, // MAXSD + CMPUNORDSD + BLENDVPD
4025 { ISD::FMAXNUM, MVT::v2f64, { 2, 7, 3, 5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
4026 { ISD::FMAXNUM, MVT::v4f64, { 3, 7, 3, 6 } }, // MAXPD + CMPUNORDPD + BLENDVPD
4027 { ISD::FSQRT, MVT::f32, { 7, 15, 1, 1 } }, // vsqrtss
4028 { ISD::FSQRT, MVT::v4f32, { 7, 15, 1, 1 } }, // vsqrtps
4029 { ISD::FSQRT, MVT::v8f32, { 14, 21, 1, 3 } }, // vsqrtps
4030 { ISD::FSQRT, MVT::f64, { 14, 21, 1, 1 } }, // vsqrtsd
4031 { ISD::FSQRT, MVT::v2f64, { 14, 21, 1, 1 } }, // vsqrtpd
4032 { ISD::FSQRT, MVT::v4f64, { 28, 35, 1, 3 } }, // vsqrtpd
4035 { ISD::ABS, MVT::v4i64, { 6, 8, 6, 12 } }, // VBLENDVPD(X,VPSUBQ(0,X),X)
4036 { ISD::ABS, MVT::v8i32, { 3, 6, 4, 5 } },
4037 { ISD::ABS, MVT::v16i16, { 3, 6, 4, 5 } },
4038 { ISD::ABS, MVT::v32i8, { 3, 6, 4, 5 } },
4039 { ISD::BITREVERSE, MVT::v4i64, { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
4040 { ISD::BITREVERSE, MVT::v2i64, { 8, 13, 10, 16 } },
4041 { ISD::BITREVERSE, MVT::v8i32, { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
4042 { ISD::BITREVERSE, MVT::v4i32, { 8, 13, 10, 16 } },
4043 { ISD::BITREVERSE, MVT::v16i16, { 17, 20, 20, 33 } }, // 2 x 128-bit Op + extract/insert
4044 { ISD::BITREVERSE, MVT::v8i16, { 8, 13, 10, 16 } },
4045 { ISD::BITREVERSE, MVT::v32i8, { 13, 15, 17, 26 } }, // 2 x 128-bit Op + extract/insert
4046 { ISD::BITREVERSE, MVT::v16i8, { 7, 7, 9, 13 } },
4047 { ISD::BSWAP, MVT::v4i64, { 5, 6, 5, 10 } },
4048 { ISD::BSWAP, MVT::v2i64, { 2, 2, 1, 3 } },
4049 { ISD::BSWAP, MVT::v8i32, { 5, 6, 5, 10 } },
4050 { ISD::BSWAP, MVT::v4i32, { 2, 2, 1, 3 } },
4051 { ISD::BSWAP, MVT::v16i16, { 5, 6, 5, 10 } },
4052 { ISD::BSWAP, MVT::v8i16, { 2, 2, 1, 3 } },
4053 { ISD::CTLZ, MVT::v4i64, { 29, 33, 49, 58 } }, // 2 x 128-bit Op + extract/insert
4054 { ISD::CTLZ, MVT::v2i64, { 14, 24, 24, 28 } },
4055 { ISD::CTLZ, MVT::v8i32, { 24, 28, 39, 48 } }, // 2 x 128-bit Op + extract/insert
4056 { ISD::CTLZ, MVT::v4i32, { 12, 20, 19, 23 } },
4057 { ISD::CTLZ, MVT::v16i16, { 19, 22, 29, 38 } }, // 2 x 128-bit Op + extract/insert
4058 { ISD::CTLZ, MVT::v8i16, { 9, 16, 14, 18 } },
4059 { ISD::CTLZ, MVT::v32i8, { 14, 15, 19, 28 } }, // 2 x 128-bit Op + extract/insert
4060 { ISD::CTLZ, MVT::v16i8, { 7, 12, 9, 13 } },
4061 { ISD::CTPOP, MVT::v4i64, { 14, 18, 19, 28 } }, // 2 x 128-bit Op + extract/insert
4062 { ISD::CTPOP, MVT::v2i64, { 7, 14, 10, 14 } },
4063 { ISD::CTPOP, MVT::v8i32, { 18, 24, 27, 36 } }, // 2 x 128-bit Op + extract/insert
4064 { ISD::CTPOP, MVT::v4i32, { 9, 20, 14, 18 } },
4065 { ISD::CTPOP, MVT::v16i16, { 16, 21, 22, 31 } }, // 2 x 128-bit Op + extract/insert
4066 { ISD::CTPOP, MVT::v8i16, { 8, 18, 11, 15 } },
4067 { ISD::CTPOP, MVT::v32i8, { 13, 15, 16, 25 } }, // 2 x 128-bit Op + extract/insert
4068 { ISD::CTPOP, MVT::v16i8, { 6, 12, 8, 12 } },
4069 { ISD::CTTZ, MVT::v4i64, { 17, 22, 24, 33 } }, // 2 x 128-bit Op + extract/insert
4070 { ISD::CTTZ, MVT::v2i64, { 9, 19, 13, 17 } },
4071 { ISD::CTTZ, MVT::v8i32, { 21, 27, 32, 41 } }, // 2 x 128-bit Op + extract/insert
4072 { ISD::CTTZ, MVT::v4i32, { 11, 24, 17, 21 } },
4073 { ISD::CTTZ, MVT::v16i16, { 18, 24, 27, 36 } }, // 2 x 128-bit Op + extract/insert
4074 { ISD::CTTZ, MVT::v8i16, { 9, 21, 14, 18 } },
4075 { ISD::CTTZ, MVT::v32i8, { 15, 18, 21, 30 } }, // 2 x 128-bit Op + extract/insert
4076 { ISD::CTTZ, MVT::v16i8, { 8, 16, 11, 15 } },
4077 { ISD::SADDSAT, MVT::v2i64, { 6, 13, 8, 11 } },
4078 { ISD::SADDSAT, MVT::v4i64, { 13, 20, 15, 25 } }, // 2 x 128-bit Op + extract/insert
4079 { ISD::SADDSAT, MVT::v8i32, { 12, 18, 14, 24 } }, // 2 x 128-bit Op + extract/insert
4080 { ISD::SADDSAT, MVT::v16i16, { 3, 3, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4081 { ISD::SADDSAT, MVT::v32i8, { 3, 3, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4082 { ISD::SMAX, MVT::v4i64, { 6, 9, 6, 12 } }, // 2 x 128-bit Op + extract/insert
4083 { ISD::SMAX, MVT::v2i64, { 3, 7, 2, 4 } },
4084 { ISD::SMAX, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4085 { ISD::SMAX, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4086 { ISD::SMAX, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4087 { ISD::SMIN, MVT::v4i64, { 6, 9, 6, 12 } }, // 2 x 128-bit Op + extract/insert
4088 { ISD::SMIN, MVT::v2i64, { 3, 7, 2, 3 } },
4089 { ISD::SMIN, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4090 { ISD::SMIN, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4091 { ISD::SMIN, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4092 { ISD::SMULO, MVT::v4i64, { 20, 20, 33, 37 } },
4093 { ISD::SMULO, MVT::v2i64, { 9, 9, 13, 17 } },
4094 { ISD::SMULO, MVT::v8i32, { 15, 20, 24, 29 } },
4095 { ISD::SMULO, MVT::v4i32, { 7, 15, 11, 13 } },
4096 { ISD::SMULO, MVT::v16i16, { 8, 14, 14, 15 } },
4097 { ISD::SMULO, MVT::v8i16, { 3, 9, 6, 6 } },
4098 { ISD::SMULO, MVT::v32i8, { 20, 20, 37, 39 } },
4099 { ISD::SMULO, MVT::v16i8, { 9, 22, 18, 21 } },
4100 { ISD::SSUBSAT, MVT::v2i64, { 7, 13, 9, 13 } },
4101 { ISD::SSUBSAT, MVT::v4i64, { 15, 21, 18, 29 } }, // 2 x 128-bit Op + extract/insert
4102 { ISD::SSUBSAT, MVT::v8i32, { 15, 19, 18, 29 } }, // 2 x 128-bit Op + extract/insert
4103 { ISD::SSUBSAT, MVT::v16i16, { 3, 3, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4104 { ISD::SSUBSAT, MVT::v32i8, { 3, 3, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4105 { ISD::UADDSAT, MVT::v2i64, { 3, 8, 6, 6 } },
4106 { ISD::UADDSAT, MVT::v4i64, { 8, 11, 14, 15 } }, // 2 x 128-bit Op + extract/insert
4107 { ISD::UADDSAT, MVT::v8i32, { 6, 6, 10, 11 } }, // 2 x 128-bit Op + extract/insert
4108 { ISD::UADDSAT, MVT::v16i16, { 3, 3, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4109 { ISD::UADDSAT, MVT::v32i8, { 3, 3, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4110 { ISD::UMAX, MVT::v4i64, { 9, 10, 11, 17 } }, // 2 x 128-bit Op + extract/insert
4111 { ISD::UMAX, MVT::v2i64, { 4, 8, 5, 7 } },
4112 { ISD::UMAX, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4113 { ISD::UMAX, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4114 { ISD::UMAX, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4115 { ISD::UMIN, MVT::v4i64, { 9, 10, 11, 17 } }, // 2 x 128-bit Op + extract/insert
4116 { ISD::UMIN, MVT::v2i64, { 4, 8, 5, 7 } },
4117 { ISD::UMIN, MVT::v8i32, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4118 { ISD::UMIN, MVT::v16i16, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4119 { ISD::UMIN, MVT::v32i8, { 4, 6, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4120 { ISD::UMULO, MVT::v4i64, { 24, 26, 39, 45 } },
4121 { ISD::UMULO, MVT::v2i64, { 10, 12, 15, 20 } },
4122 { ISD::UMULO, MVT::v8i32, { 14, 15, 23, 28 } },
4123 { ISD::UMULO, MVT::v4i32, { 7, 12, 11, 13 } },
4124 { ISD::UMULO, MVT::v16i16, { 7, 11, 13, 14 } },
4125 { ISD::UMULO, MVT::v8i16, { 3, 8, 6, 6 } },
4126 { ISD::UMULO, MVT::v32i8, { 19, 19, 35, 37 } },
4127 { ISD::UMULO, MVT::v16i8, { 9, 19, 17, 20 } },
4128 { ISD::USUBSAT, MVT::v2i64, { 3, 7, 6, 6 } },
4129 { ISD::USUBSAT, MVT::v4i64, { 8, 10, 14, 15 } }, // 2 x 128-bit Op + extract/insert
4130 { ISD::USUBSAT, MVT::v8i32, { 4, 4, 7, 8 } }, // 2 x 128-bit Op + extract/insert
4131 { ISD::USUBSAT, MVT::v8i32, { 3, 3, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4132 { ISD::USUBSAT, MVT::v16i16, { 3, 3, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4133 { ISD::USUBSAT, MVT::v32i8, { 3, 3, 5, 6 } }, // 2 x 128-bit Op + extract/insert
4134 { ISD::FMAXNUM, MVT::f32, { 3, 6, 3, 5 } }, // MAXSS + CMPUNORDSS + BLENDVPS
4135 { ISD::FMAXNUM, MVT::v4f32, { 3, 6, 3, 5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
4136 { ISD::FMAXNUM, MVT::v8f32, { 5, 7, 3, 10 } }, // MAXPS + CMPUNORDPS + BLENDVPS
4137 { ISD::FMAXNUM, MVT::f64, { 3, 6, 3, 5 } }, // MAXSD + CMPUNORDSD + BLENDVPD
4138 { ISD::FMAXNUM, MVT::v2f64, { 3, 6, 3, 5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
4139 { ISD::FMAXNUM, MVT::v4f64, { 5, 7, 3, 10 } }, // MAXPD + CMPUNORDPD + BLENDVPD
4140 { ISD::FSQRT, MVT::f32, { 21, 21, 1, 1 } }, // vsqrtss
4141 { ISD::FSQRT, MVT::v4f32, { 21, 21, 1, 1 } }, // vsqrtps
4142 { ISD::FSQRT, MVT::v8f32, { 42, 42, 1, 3 } }, // vsqrtps
4143 { ISD::FSQRT, MVT::f64, { 27, 27, 1, 1 } }, // vsqrtsd
4144 { ISD::FSQRT, MVT::v2f64, { 27, 27, 1, 1 } }, // vsqrtpd
4145 { ISD::FSQRT, MVT::v4f64, { 54, 54, 1, 3 } }, // vsqrtpd
4148 { ISD::BITREVERSE, MVT::i8, { 3, 3, 3, 4 } }, // gf2p8affineqb
4149 { ISD::BITREVERSE, MVT::i16, { 3, 3, 4, 6 } }, // gf2p8affineqb
4150 { ISD::BITREVERSE, MVT::i32, { 3, 3, 4, 5 } }, // gf2p8affineqb
4151 { ISD::BITREVERSE, MVT::i64, { 3, 3, 4, 6 } }, // gf2p8affineqb
4152 { ISD::BITREVERSE, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
4153 { ISD::BITREVERSE, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
4154 { ISD::BITREVERSE, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
4155 { ISD::BITREVERSE, MVT::v8i16, { 1, 8, 2, 4 } }, // gf2p8affineqb
4156 { ISD::BITREVERSE, MVT::v16i16, { 1, 9, 2, 4 } }, // gf2p8affineqb
4157 { ISD::BITREVERSE, MVT::v32i16, { 1, 9, 2, 4 } }, // gf2p8affineqb
4158 { ISD::BITREVERSE, MVT::v4i32, { 1, 8, 2, 4 } }, // gf2p8affineqb
4159 { ISD::BITREVERSE, MVT::v8i32, { 1, 9, 2, 4 } }, // gf2p8affineqb
4160 { ISD::BITREVERSE, MVT::v16i32, { 1, 9, 2, 4 } }, // gf2p8affineqb
4161 { ISD::BITREVERSE, MVT::v2i64, { 1, 8, 2, 4 } }, // gf2p8affineqb
4162 { ISD::BITREVERSE, MVT::v4i64, { 1, 9, 2, 4 } }, // gf2p8affineqb
4163 { ISD::BITREVERSE, MVT::v8i64, { 1, 9, 2, 4 } }, // gf2p8affineqb
4169 { ISD::FSQRT, MVT::f32, { 19, 20, 1, 1 } }, // sqrtss
4170 { ISD::FSQRT, MVT::v4f32, { 37, 41, 1, 5 } }, // sqrtps
4171 { ISD::FSQRT, MVT::f64, { 34, 35, 1, 1 } }, // sqrtsd
4172 { ISD::FSQRT, MVT::v2f64, { 67, 71, 1, 5 } }, // sqrtpd
4175 { ISD::BSWAP, MVT::v2i64, { 5, 5, 1, 5 } },
4176 { ISD::BSWAP, MVT::v4i32, { 5, 5, 1, 5 } },
4177 { ISD::BSWAP, MVT::v8i16, { 5, 5, 1, 5 } },
4178 { ISD::FSQRT, MVT::f32, { 20, 20, 1, 1 } }, // sqrtss
4179 { ISD::FSQRT, MVT::v4f32, { 40, 41, 1, 5 } }, // sqrtps
4180 { ISD::FSQRT, MVT::f64, { 35, 35, 1, 1 } }, // sqrtsd
4181 { ISD::FSQRT, MVT::v2f64, { 70, 71, 1, 5 } }, // sqrtpd
4184 { ISD::FMAXNUM, MVT::f32, { 5, 5, 7, 7 } }, // MAXSS + CMPUNORDSS + BLENDVPS
4185 { ISD::FMAXNUM, MVT::v4f32, { 4, 4, 4, 5 } }, // MAXPS + CMPUNORDPS + BLENDVPS
4186 { ISD::FMAXNUM, MVT::f64, { 5, 5, 7, 7 } }, // MAXSD + CMPUNORDSD + BLENDVPD
4187 { ISD::FMAXNUM, MVT::v2f64, { 4, 4, 4, 5 } }, // MAXPD + CMPUNORDPD + BLENDVPD
4188 { ISD::FSQRT, MVT::f32, { 18, 18, 1, 1 } }, // Nehalem from http://www.agner.org/
4189 { ISD::FSQRT, MVT::v4f32, { 18, 18, 1, 1 } }, // Nehalem from http://www.agner.org/
4192 { ISD::ABS, MVT::v2i64, { 3, 4, 3, 5 } }, // BLENDVPD(X,PSUBQ(0,X),X)
4193 { ISD::SADDSAT, MVT::v2i64, { 10, 14, 17, 21 } },
4194 { ISD::SADDSAT, MVT::v4i32, { 5, 11, 8, 10 } },
4195 { ISD::SSUBSAT, MVT::v2i64, { 12, 19, 25, 29 } },
4196 { ISD::SSUBSAT, MVT::v4i32, { 6, 14, 10, 12 } },
4197 { ISD::SMAX, MVT::v2i64, { 3, 7, 2, 3 } },
4198 { ISD::SMAX, MVT::v4i32, { 1, 1, 1, 1 } },
4199 { ISD::SMAX, MVT::v16i8, { 1, 1, 1, 1 } },
4200 { ISD::SMIN, MVT::v2i64, { 3, 7, 2, 3 } },
4201 { ISD::SMIN, MVT::v4i32, { 1, 1, 1, 1 } },
4202 { ISD::SMIN, MVT::v16i8, { 1, 1, 1, 1 } },
4203 { ISD::SMULO, MVT::v2i64, { 9, 11, 13, 17 } },
4204 { ISD::SMULO, MVT::v4i32, { 20, 24, 13, 19 } },
4205 { ISD::SMULO, MVT::v8i16, { 5, 9, 8, 8 } },
4206 { ISD::SMULO, MVT::v16i8, { 13, 22, 24, 25 } },
4207 { ISD::UADDSAT, MVT::v2i64, { 6, 13, 14, 14 } },
4208 { ISD::UADDSAT, MVT::v4i32, { 2, 2, 4, 4 } },
4209 { ISD::USUBSAT, MVT::v2i64, { 6, 10, 14, 14 } },
4210 { ISD::USUBSAT, MVT::v4i32, { 1, 2, 2, 2 } },
4211 { ISD::UMAX, MVT::v2i64, { 2, 11, 6, 7 } },
4212 { ISD::UMAX, MVT::v4i32, { 1, 1, 1, 1 } },
4213 { ISD::UMAX, MVT::v8i16, { 1, 1, 1, 1 } },
4214 { ISD::UMIN, MVT::v2i64, { 2, 11, 6, 7 } },
4215 { ISD::UMIN, MVT::v4i32, { 1, 1, 1, 1 } },
4216 { ISD::UMIN, MVT::v8i16, { 1, 1, 1, 1 } },
4217 { ISD::UMULO, MVT::v2i64, { 14, 20, 15, 20 } },
4218 { ISD::UMULO, MVT::v4i32, { 19, 22, 12, 18 } },
4219 { ISD::UMULO, MVT::v8i16, { 4, 9, 7, 7 } },
4220 { ISD::UMULO, MVT::v16i8, { 13, 19, 18, 20 } },
4223 { ISD::ABS, MVT::v4i32, { 1, 2, 1, 1 } },
4224 { ISD::ABS, MVT::v8i16, { 1, 2, 1, 1 } },
4225 { ISD::ABS, MVT::v16i8, { 1, 2, 1, 1 } },
4226 { ISD::BITREVERSE, MVT::v2i64, { 16, 20, 11, 21 } },
4227 { ISD::BITREVERSE, MVT::v4i32, { 16, 20, 11, 21 } },
4228 { ISD::BITREVERSE, MVT::v8i16, { 16, 20, 11, 21 } },
4229 { ISD::BITREVERSE, MVT::v16i8, { 11, 12, 10, 16 } },
4230 { ISD::BSWAP, MVT::v2i64, { 2, 3, 1, 5 } },
4231 { ISD::BSWAP, MVT::v4i32, { 2, 3, 1, 5 } },
4232 { ISD::BSWAP, MVT::v8i16, { 2, 3, 1, 5 } },
4233 { ISD::CTLZ, MVT::v2i64, { 18, 28, 28, 35 } },
4234 { ISD::CTLZ, MVT::v4i32, { 15, 20, 22, 28 } },
4235 { ISD::CTLZ, MVT::v8i16, { 13, 17, 16, 22 } },
4236 { ISD::CTLZ, MVT::v16i8, { 11, 15, 10, 16 } },
4237 { ISD::CTPOP, MVT::v2i64, { 13, 19, 12, 18 } },
4238 { ISD::CTPOP, MVT::v4i32, { 18, 24, 16, 22 } },
4239 { ISD::CTPOP, MVT::v8i16, { 13, 18, 14, 20 } },
4240 { ISD::CTPOP, MVT::v16i8, { 11, 12, 10, 16 } },
4241 { ISD::CTTZ, MVT::v2i64, { 13, 25, 15, 22 } },
4242 { ISD::CTTZ, MVT::v4i32, { 18, 26, 19, 25 } },
4243 { ISD::CTTZ, MVT::v8i16, { 13, 20, 17, 23 } },
4244 { ISD::CTTZ, MVT::v16i8, { 11, 16, 13, 19 } }
4247 { ISD::ABS, MVT::v2i64, { 3, 6, 5, 5 } },
4248 { ISD::ABS, MVT::v4i32, { 1, 4, 4, 4 } },
4249 { ISD::ABS, MVT::v8i16, { 1, 2, 3, 3 } },
4250 { ISD::ABS, MVT::v16i8, { 1, 2, 3, 3 } },
4251 { ISD::BITREVERSE, MVT::v2i64, { 16, 20, 32, 32 } },
4252 { ISD::BITREVERSE, MVT::v4i32, { 16, 20, 30, 30 } },
4253 { ISD::BITREVERSE, MVT::v8i16, { 16, 20, 25, 25 } },
4254 { ISD::BITREVERSE, MVT::v16i8, { 11, 12, 21, 21 } },
4255 { ISD::BSWAP, MVT::v2i64, { 5, 6, 11, 11 } },
4256 { ISD::BSWAP, MVT::v4i32, { 5, 5, 9, 9 } },
4257 { ISD::BSWAP, MVT::v8i16, { 5, 5, 4, 5 } },
4258 { ISD::CTLZ, MVT::v2i64, { 10, 45, 36, 38 } },
4259 { ISD::CTLZ, MVT::v4i32, { 10, 45, 38, 40 } },
4260 { ISD::CTLZ, MVT::v8i16, { 9, 38, 32, 34 } },
4261 { ISD::CTLZ, MVT::v16i8, { 8, 39, 29, 32 } },
4262 { ISD::CTPOP, MVT::v2i64, { 12, 26, 16, 18 } },
4263 { ISD::CTPOP, MVT::v4i32, { 15, 29, 21, 23 } },
4264 { ISD::CTPOP, MVT::v8i16, { 13, 25, 18, 20 } },
4265 { ISD::CTPOP, MVT::v16i8, { 10, 21, 14, 16 } },
4266 { ISD::CTTZ, MVT::v2i64, { 14, 28, 19, 21 } },
4267 { ISD::CTTZ, MVT::v4i32, { 18, 31, 24, 26 } },
4268 { ISD::CTTZ, MVT::v8i16, { 16, 27, 21, 23 } },
4269 { ISD::CTTZ, MVT::v16i8, { 13, 23, 17, 19 } },
4270 { ISD::SADDSAT, MVT::v2i64, { 12, 14, 24, 24 } },
4271 { ISD::SADDSAT, MVT::v4i32, { 6, 11, 11, 12 } },
4272 { ISD::SADDSAT, MVT::v8i16, { 1, 2, 1, 1 } },
4273 { ISD::SADDSAT, MVT::v16i8, { 1, 2, 1, 1 } },
4274 { ISD::SMAX, MVT::v2i64, { 4, 8, 15, 15 } },
4275 { ISD::SMAX, MVT::v4i32, { 2, 4, 5, 5 } },
4276 { ISD::SMAX, MVT::v8i16, { 1, 1, 1, 1 } },
4277 { ISD::SMAX, MVT::v16i8, { 2, 4, 5, 5 } },
4278 { ISD::SMIN, MVT::v2i64, { 4, 8, 15, 15 } },
4279 { ISD::SMIN, MVT::v4i32, { 2, 4, 5, 5 } },
4280 { ISD::SMIN, MVT::v8i16, { 1, 1, 1, 1 } },
4281 { ISD::SMIN, MVT::v16i8, { 2, 4, 5, 5 } },
4282 { ISD::SMULO, MVT::v2i64, { 30, 33, 13, 23 } },
4283 { ISD::SMULO, MVT::v4i32, { 20, 24, 23, 23 } },
4284 { ISD::SMULO, MVT::v8i16, { 5, 10, 8, 8 } },
4285 { ISD::SMULO, MVT::v16i8, { 13, 23, 24, 25 } },
4286 { ISD::SSUBSAT, MVT::v2i64, { 16, 19, 31, 31 } },
4287 { ISD::SSUBSAT, MVT::v4i32, { 6, 14, 12, 13 } },
4288 { ISD::SSUBSAT, MVT::v8i16, { 1, 2, 1, 1 } },
4289 { ISD::SSUBSAT, MVT::v16i8, { 1, 2, 1, 1 } },
4290 { ISD::UADDSAT, MVT::v2i64, { 7, 13, 14, 14 } },
4291 { ISD::UADDSAT, MVT::v4i32, { 4, 5, 7, 7 } },
4292 { ISD::UADDSAT, MVT::v8i16, { 1, 2, 1, 1 } },
4293 { ISD::UADDSAT, MVT::v16i8, { 1, 2, 1, 1 } },
4294 { ISD::UMAX, MVT::v2i64, { 4, 8, 15, 15 } },
4295 { ISD::UMAX, MVT::v4i32, { 2, 5, 8, 8 } },
4296 { ISD::UMAX, MVT::v8i16, { 1, 3, 3, 3 } },
4297 { ISD::UMAX, MVT::v16i8, { 1, 1, 1, 1 } },
4298 { ISD::UMIN, MVT::v2i64, { 4, 8, 15, 15 } },
4299 { ISD::UMIN, MVT::v4i32, { 2, 5, 8, 8 } },
4300 { ISD::UMIN, MVT::v8i16, { 1, 3, 3, 3 } },
4301 { ISD::UMIN, MVT::v16i8, { 1, 1, 1, 1 } },
4302 { ISD::UMULO, MVT::v2i64, { 30, 33, 15, 29 } },
4303 { ISD::UMULO, MVT::v4i32, { 19, 22, 14, 18 } },
4304 { ISD::UMULO, MVT::v8i16, { 4, 9, 7, 7 } },
4305 { ISD::UMULO, MVT::v16i8, { 13, 19, 20, 20 } },
4306 { ISD::USUBSAT, MVT::v2i64, { 7, 10, 14, 14 } },
4307 { ISD::USUBSAT, MVT::v4i32, { 4, 4, 7, 7 } },
4308 { ISD::USUBSAT, MVT::v8i16, { 1, 2, 1, 1 } },
4309 { ISD::USUBSAT, MVT::v16i8, { 1, 2, 1, 1 } },
4310 { ISD::FMAXNUM, MVT::f64, { 5, 5, 7, 7 } },
4311 { ISD::FMAXNUM, MVT::v2f64, { 4, 6, 6, 6 } },
4312 { ISD::FSQRT, MVT::f64, { 32, 32, 1, 1 } }, // Nehalem from http://www.agner.org/
4313 { ISD::FSQRT, MVT::v2f64, { 32, 32, 1, 1 } }, // Nehalem from http://www.agner.org/
4316 { ISD::FMAXNUM, MVT::f32, { 5, 5, 7, 7 } },
4317 { ISD::FMAXNUM, MVT::v4f32, { 4, 6, 6, 6 } },
4318 { ISD::FSQRT, MVT::f32, { 28, 30, 1, 2 } }, // Pentium III from http://www.agner.org/
4319 { ISD::FSQRT, MVT::v4f32, { 56, 56, 1, 2 } }, // Pentium III from http://www.agner.org/
4322 { ISD::CTTZ, MVT::i64, { 1, 1, 1, 1 } },
4325 { ISD::CTTZ, MVT::i32, { 1, 1, 1, 1 } },
4326 { ISD::CTTZ, MVT::i16, { 2, 1, 1, 1 } },
4327 { ISD::CTTZ, MVT::i8, { 2, 1, 1, 1 } },
4330 { ISD::CTLZ, MVT::i64, { 1, 1, 1, 1 } },
4333 { ISD::CTLZ, MVT::i32, { 1, 1, 1, 1 } },
4334 { ISD::CTLZ, MVT::i16, { 2, 1, 1, 1 } },
4335 { ISD::CTLZ, MVT::i8, { 2, 1, 1, 1 } },
4338 { ISD::CTPOP, MVT::i64, { 1, 1, 1, 1 } }, // popcnt
4341 { ISD::CTPOP, MVT::i32, { 1, 1, 1, 1 } }, // popcnt
4342 { ISD::CTPOP, MVT::i16, { 1, 1, 2, 2 } }, // popcnt(zext())
4343 { ISD::CTPOP, MVT::i8, { 1, 1, 2, 2 } }, // popcnt(zext())
4346 { ISD::ABS, MVT::i64, { 1, 2, 3, 3 } }, // SUB+CMOV
4347 { ISD::BITREVERSE, MVT::i64, { 10, 12, 20, 22 } },
4348 { ISD::BSWAP, MVT::i64, { 1, 2, 1, 2 } },
4349 { ISD::CTLZ, MVT::i64, { 1, 2, 3, 3 } }, // MOV+BSR+XOR
4350 { ISD::CTLZ, MVT::i32, { 1, 2, 3, 3 } }, // MOV+BSR+XOR
4351 { ISD::CTLZ, MVT::i16, { 2, 2, 3, 3 } }, // MOV+BSR+XOR
4352 { ISD::CTLZ, MVT::i8, { 2, 2, 4, 3 } }, // MOV+BSR+XOR
4353 { ISD::CTLZ_ZERO_UNDEF, MVT::i64,{ 1, 2, 2, 2 } }, // BSR+XOR
4354 { ISD::CTTZ, MVT::i64, { 1, 2, 2, 2 } }, // MOV+BSF
4355 { ISD::CTTZ, MVT::i32, { 1, 2, 2, 2 } }, // MOV+BSF
4356 { ISD::CTTZ, MVT::i16, { 2, 2, 2, 2 } }, // MOV+BSF
4357 { ISD::CTTZ, MVT::i8, { 2, 2, 2, 2 } }, // MOV+BSF
4358 { ISD::CTTZ_ZERO_UNDEF, MVT::i64,{ 1, 2, 1, 2 } }, // BSF
4359 { ISD::CTPOP, MVT::i64, { 10, 6, 19, 19 } },
4360 { ISD::ROTL, MVT::i64, { 2, 3, 1, 3 } },
4361 { ISD::ROTR, MVT::i64, { 2, 3, 1, 3 } },
4363 { ISD::FSHL, MVT::i64, { 4, 4, 1, 4 } },
4364 { ISD::SADDSAT, MVT::i64, { 4, 4, 7, 10 } },
4365 { ISD::SSUBSAT, MVT::i64, { 4, 5, 8, 11 } },
4366 { ISD::UADDSAT, MVT::i64, { 2, 3, 4, 7 } },
4367 { ISD::USUBSAT, MVT::i64, { 2, 3, 4, 7 } },
4368 { ISD::SMAX, MVT::i64, { 1, 3, 2, 3 } },
4369 { ISD::SMIN, MVT::i64, { 1, 3, 2, 3 } },
4370 { ISD::UMAX, MVT::i64, { 1, 3, 2, 3 } },
4371 { ISD::UMIN, MVT::i64, { 1, 3, 2, 3 } },
4372 { ISD::SADDO, MVT::i64, { 2, 2, 4, 6 } },
4373 { ISD::UADDO, MVT::i64, { 2, 2, 4, 6 } },
4374 { ISD::SMULO, MVT::i64, { 4, 4, 4, 6 } },
4375 { ISD::UMULO, MVT::i64, { 8, 8, 4, 7 } },
4378 { ISD::ABS, MVT::i32, { 1, 2, 3, 3 } }, // SUB+XOR+SRA or SUB+CMOV
4379 { ISD::ABS, MVT::i16, { 2, 2, 3, 3 } }, // SUB+XOR+SRA or SUB+CMOV
4380 { ISD::ABS, MVT::i8, { 2, 4, 4, 3 } }, // SUB+XOR+SRA
4381 { ISD::BITREVERSE, MVT::i32, { 9, 12, 17, 19 } },
4382 { ISD::BITREVERSE, MVT::i16, { 9, 12, 17, 19 } },
4383 { ISD::BITREVERSE, MVT::i8, { 7, 9, 13, 14 } },
4384 { ISD::BSWAP, MVT::i32, { 1, 1, 1, 1 } },
4385 { ISD::BSWAP, MVT::i16, { 1, 2, 1, 2 } }, // ROL
4386 { ISD::CTLZ, MVT::i32, { 2, 2, 4, 5 } }, // BSR+XOR or BSR+XOR+CMOV
4387 { ISD::CTLZ, MVT::i16, { 2, 2, 4, 5 } }, // BSR+XOR or BSR+XOR+CMOV
4388 { ISD::CTLZ, MVT::i8, { 2, 2, 5, 6 } }, // BSR+XOR or BSR+XOR+CMOV
4389 { ISD::CTLZ_ZERO_UNDEF, MVT::i32,{ 1, 2, 2, 2 } }, // BSR+XOR
4390 { ISD::CTLZ_ZERO_UNDEF, MVT::i16,{ 2, 2, 2, 2 } }, // BSR+XOR
4391 { ISD::CTLZ_ZERO_UNDEF, MVT::i8, { 2, 2, 3, 3 } }, // BSR+XOR
4392 { ISD::CTTZ, MVT::i32, { 2, 2, 3, 3 } }, // TEST+BSF+CMOV/BRANCH
4393 { ISD::CTTZ, MVT::i16, { 2, 2, 2, 3 } }, // TEST+BSF+CMOV/BRANCH
4394 { ISD::CTTZ, MVT::i8, { 2, 2, 2, 3 } }, // TEST+BSF+CMOV/BRANCH
4395 { ISD::CTTZ_ZERO_UNDEF, MVT::i32,{ 1, 2, 1, 2 } }, // BSF
4396 { ISD::CTTZ_ZERO_UNDEF, MVT::i16,{ 2, 2, 1, 2 } }, // BSF
4397 { ISD::CTTZ_ZERO_UNDEF, MVT::i8, { 2, 2, 1, 2 } }, // BSF
4398 { ISD::CTPOP, MVT::i32, { 8, 7, 15, 15 } },
4399 { ISD::CTPOP, MVT::i16, { 9, 8, 17, 17 } },
4400 { ISD::CTPOP, MVT::i8, { 7, 6, 6, 6 } },
4401 { ISD::ROTL, MVT::i32, { 2, 3, 1, 3 } },
4402 { ISD::ROTL, MVT::i16, { 2, 3, 1, 3 } },
4403 { ISD::ROTL, MVT::i8, { 2, 3, 1, 3 } },
4404 { ISD::ROTR, MVT::i32, { 2, 3, 1, 3 } },
4405 { ISD::ROTR, MVT::i16, { 2, 3, 1, 3 } },
4406 { ISD::ROTR, MVT::i8, { 2, 3, 1, 3 } },
4410 { ISD::FSHL, MVT::i32, { 4, 4, 1, 4 } },
4411 { ISD::FSHL, MVT::i16, { 4, 4, 2, 5 } },
4412 { ISD::FSHL, MVT::i8, { 4, 4, 2, 5 } },
4413 { ISD::SADDSAT, MVT::i32, { 3, 4, 6, 9 } },
4414 { ISD::SADDSAT, MVT::i16, { 4, 4, 7, 10 } },
4415 { ISD::SADDSAT, MVT::i8, { 4, 5, 8, 11 } },
4416 { ISD::SSUBSAT, MVT::i32, { 4, 4, 7, 10 } },
4417 { ISD::SSUBSAT, MVT::i16, { 4, 4, 7, 10 } },
4418 { ISD::SSUBSAT, MVT::i8, { 4, 5, 8, 11 } },
4419 { ISD::UADDSAT, MVT::i32, { 2, 3, 4, 7 } },
4420 { ISD::UADDSAT, MVT::i16, { 2, 3, 4, 7 } },
4421 { ISD::UADDSAT, MVT::i8, { 3, 3, 5, 8 } },
4422 { ISD::USUBSAT, MVT::i32, { 2, 3, 4, 7 } },
4423 { ISD::USUBSAT, MVT::i16, { 2, 3, 4, 7 } },
4424 { ISD::USUBSAT, MVT::i8, { 3, 3, 5, 8 } },
4425 { ISD::SMAX, MVT::i32, { 1, 2, 2, 3 } },
4426 { ISD::SMAX, MVT::i16, { 1, 4, 2, 4 } },
4427 { ISD::SMAX, MVT::i8, { 1, 4, 2, 4 } },
4428 { ISD::SMIN, MVT::i32, { 1, 2, 2, 3 } },
4429 { ISD::SMIN, MVT::i16, { 1, 4, 2, 4 } },
4430 { ISD::SMIN, MVT::i8, { 1, 4, 2, 4 } },
4431 { ISD::UMAX, MVT::i32, { 1, 2, 2, 3 } },
4432 { ISD::UMAX, MVT::i16, { 1, 4, 2, 4 } },
4433 { ISD::UMAX, MVT::i8, { 1, 4, 2, 4 } },
4434 { ISD::UMIN, MVT::i32, { 1, 2, 2, 3 } },
4435 { ISD::UMIN, MVT::i16, { 1, 4, 2, 4 } },
4436 { ISD::UMIN, MVT::i8, { 1, 4, 2, 4 } },
4437 { ISD::SADDO, MVT::i32, { 2, 2, 4, 6 } },
4438 { ISD::SADDO, MVT::i16, { 2, 2, 4, 6 } },
4439 { ISD::SADDO, MVT::i8, { 2, 2, 4, 6 } },
4440 { ISD::UADDO, MVT::i32, { 2, 2, 4, 6 } },
4441 { ISD::UADDO, MVT::i16, { 2, 2, 4, 6 } },
4442 { ISD::UADDO, MVT::i8, { 2, 2, 4, 6 } },
4443 { ISD::SMULO, MVT::i32, { 2, 2, 4, 6 } },
4444 { ISD::SMULO, MVT::i16, { 5, 5, 4, 6 } },
4445 { ISD::SMULO, MVT::i8, { 6, 6, 4, 6 } },
4446 { ISD::UMULO, MVT::i32, { 6, 6, 4, 8 } },
4447 { ISD::UMULO, MVT::i16, { 6, 6, 4, 9 } },
4448 { ISD::UMULO, MVT::i8, { 6, 6, 4, 6 } },
4454 unsigned ISD = ISD::DELETED_NODE;
4459 ISD = ISD::ABS;
4462 ISD = ISD::BITREVERSE;
4465 ISD = ISD::BSWAP;
4468 ISD = ISD::CTLZ;
4471 ISD = ISD::CTPOP;
4474 ISD = ISD::CTTZ;
4477 ISD = ISD::FSHL;
4481 ISD = ISD::ROTL;
4487 ISD = X86ISD::VROTLI;
4493 ISD = ISD::FSHL;
4497 ISD = ISD::ROTR;
4503 ISD = X86ISD::VROTLI;
4518 ISD = ISD::FMAXNUM;
4521 ISD = ISD::SADDSAT;
4524 ISD = ISD::SMAX;
4527 ISD = ISD::SMIN;
4530 ISD = ISD::SSUBSAT;
4533 ISD = ISD::UADDSAT;
4536 ISD = ISD::UMAX;
4539 ISD = ISD::UMIN;
4542 ISD = ISD::USUBSAT;
4545 ISD = ISD::FSQRT;
4550 ISD = ISD::SADDO;
4556 ISD = ISD::UADDO;
4560 ISD = ISD::SMULO;
4564 ISD = ISD::UMULO;
4569 if (ISD != ISD::DELETED_NODE) {
4570 auto adjustTableCost = [&](int ISD, unsigned Cost,
4579 if (ISD == ISD::FMAXNUM || ISD == ISD::FMINNUM) {
4586 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) {
4606 if (((ISD == ISD::CTTZ && !ST->hasBMI()) ||
4607 (ISD == ISD::CTLZ && !ST->hasLZCNT())) &&
4612 ISD = ISD == ISD::CTTZ ? ISD::CTTZ_ZERO_UNDEF : ISD::CTLZ_ZERO_UNDEF;
4616 if (ISD == ISD::FSQRT && CostKind == TTI::TCK_CodeSize)
4620 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy))
4622 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4625 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
4627 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4630 if (const auto *Entry = CostTableLookup(AVX512VBMI2CostTbl, ISD, MTy))
4632 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4635 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy))
4637 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4640 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy))
4642 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4645 if (const auto *Entry = CostTableLookup(GFNICostTbl, ISD, MTy))
4647 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4650 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy))
4652 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4655 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
4657 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4660 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
4662 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4665 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
4667 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4670 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
4672 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4675 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
4677 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4680 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
4682 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4685 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
4687 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4690 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy))
4692 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4695 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
4697 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4700 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
4702 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4706 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy))
4708 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4710 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy))
4712 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4717 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy))
4719 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4721 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy))
4723 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4728 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy))
4730 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4732 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy))
4734 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4738 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
4740 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4742 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
4744 return adjustTableCost(Entry->ISD, *KindCost, LT, ICA.getFlags());
4773 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 },
4774 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 },
4775 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 },
4776 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 }
4884 int ISD = TLI->InstructionOpcodeToISD(Opcode);
4885 assert(ISD && "Unexpected vector opcode");
4887 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy))
4937 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much
4938 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT.
5482 { ISD::FADD, MVT::v2f64, 3 },
5483 { ISD::ADD, MVT::v2i64, 5 },
5487 { ISD::FADD, MVT::v2f64, 2 },
5488 { ISD::FADD, MVT::v2f32, 2 },
5489 { ISD::FADD, MVT::v4f32, 4 },
5490 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
5491 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32
5492 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
5493 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3".
5494 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3".
5495 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
5496 { ISD::ADD, MVT::v2i8, 2 },
5497 { ISD::ADD, MVT::v4i8, 2 },
5498 { ISD::ADD, MVT::v8i8, 2 },
5499 { ISD::ADD, MVT::v16i8, 3 },
5503 { ISD::FADD, MVT::v4f64, 3 },
5504 { ISD::FADD, MVT::v4f32, 3 },
5505 { ISD::FADD, MVT::v8f32, 4 },
5506 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
5507 { ISD::ADD, MVT::v4i64, 3 },
5508 { ISD::ADD, MVT::v8i32, 5 },
5509 { ISD::ADD, MVT::v16i16, 5 },
5510 { ISD::ADD, MVT::v32i8, 4 },
5513 int ISD = TLI->InstructionOpcodeToISD(Opcode);
5514 assert(ISD && "Invalid opcode");
5523 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
5527 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5531 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
5542 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) {
5562 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
5566 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5570 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
5576 { ISD::AND, MVT::v2i1, 3 },
5577 { ISD::AND, MVT::v4i1, 5 },
5578 { ISD::AND, MVT::v8i1, 7 },
5579 { ISD::AND, MVT::v16i1, 9 },
5580 { ISD::AND, MVT::v32i1, 11 },
5581 { ISD::AND, MVT::v64i1, 13 },
5582 { ISD::OR, MVT::v2i1, 3 },
5583 { ISD::OR, MVT::v4i1, 5 },
5584 { ISD::OR, MVT::v8i1, 7 },
5585 { ISD::OR, MVT::v16i1, 9 },
5586 { ISD::OR, MVT::v32i1, 11 },
5587 { ISD::OR, MVT::v64i1, 13 },
5591 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp
5592 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp
5593 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp
5594 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp
5598 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp
5599 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp
5600 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
5601 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp
5602 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp
5603 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp
5604 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
5605 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
5609 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp
5610 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp
5611 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp
5612 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp
5613 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp
5614 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp
5615 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp
5616 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp
5632 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy))
5635 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy))
5638 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy))
5641 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy))
5736 int ISD;
5738 ISD = (IID == Intrinsic::umin || IID == Intrinsic::umax) ? ISD::UMIN
5739 : ISD::SMIN;
5743 ISD = (IID == Intrinsic::minnum || IID == Intrinsic::maxnum)
5744 ? ISD::FMINNUM
5745 : ISD::FMINIMUM;
5752 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw
5753 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw
5754 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw
5758 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2
5759 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2
5760 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2
5761 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2
5762 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor
5763 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax
5764 {ISD::SMIN, MVT::v2i8, 3}, // pminsb
5765 {ISD::SMIN, MVT::v4i8, 5}, // pminsb
5766 {ISD::SMIN, MVT::v8i8, 7}, // pminsb
5767 {ISD::SMIN, MVT::v16i8, 6},
5768 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2
5769 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2
5770 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2
5771 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax
5775 {ISD::SMIN, MVT::v16i16, 6},
5776 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax
5777 {ISD::SMIN, MVT::v32i8, 8},
5778 {ISD::UMIN, MVT::v32i8, 8},
5782 {ISD::SMIN, MVT::v32i16, 8},
5783 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax
5784 {ISD::SMIN, MVT::v64i8, 10},
5785 {ISD::UMIN, MVT::v64i8, 10},
5795 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
5799 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5803 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
5807 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
5827 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
5831 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
5835 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
5839 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
6419 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);