Lines Matching defs:isKill

1161                                   bool &isKill, MachineOperand &ImplicitOp,
1171 isKill = MI.killsRegister(SrcReg, /*TRI=*/nullptr);
1201 .addReg(SrcReg, getKillRegState(isKill));
1204 isKill = true;
1263 bool IsKill = MI.getOperand(1).isKill();
1309 bool IsKill2 = MI.getOperand(2).isKill();
1468 bool isKill;
1470 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1478 .addReg(SrcReg, getKillRegState(isKill))
1506 bool isKill;
1508 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1514 .addReg(SrcReg, getKillRegState(isKill));
1532 bool isKill;
1534 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1540 .addReg(SrcReg, getKillRegState(isKill));
1576 bool isKill;
1581 isKill = isKill2;
1584 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1595 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1626 bool isKill;
1628 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1634 .addReg(SrcReg, getKillRegState(isKill));
1666 bool isKill;
1668 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1674 .addReg(SrcReg, getKillRegState(isKill));
2026 if (Op.isReg() && (Op.isDead() || Op.isKill()))
4748 bool isKill) const {
4761 .addReg(Reg, getKillRegState(isKill));
4786 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
4801 loadStoreTileReg(MBB, MI, Opc, SrcReg, FrameIdx, isKill);
4804 .addReg(SrcReg, getKillRegState(isKill))
5832 /*isKill=*/false,
8483 // Address operands cannot be marked isKill.
8507 getKillRegState(ImpOp.isKill()) |
10545 if (MI.isDebugInstr() || MI.isKill())
10861 bool IsKill = Root.getOperand(1).isKill();