Lines Matching defs:NewMI
1005 MachineInstr &NewMI = *std::prev(I);
1006 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1335 MachineInstr *NewMI = MIB;
1343 LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1345 LV->getVarInfo(InRegLEA2).Kills.push_back(NewMI);
1361 SlotIndex NewIdx = LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
1429 MachineInstr *NewMI = nullptr;
1450 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1483 NewMI = MIB;
1487 LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1518 NewMI = addOffset(MIB, 1);
1522 LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1544 NewMI = addOffset(MIB, -1);
1548 LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1595 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1600 LV->getVarInfo(SrcReg2).Kills.push_back(NewMI);
1602 LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1617 NewMI = addOffset(
1638 NewMI = addOffset(MIB, MI.getOperand(2));
1642 LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1678 NewMI = addOffset(MIB, -Imm);
1682 LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
1697 NewMI = addOffset(MIB, -Imm);
1871 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
2010 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
2020 if (!NewMI)
2027 LV->replaceKillInstruction(Op.getReg(), MI, *NewMI);
2032 MBB.insert(MI.getIterator(), NewMI); // Insert the new inst
2035 LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
2042 return NewMI;
2282 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2286 return std::exchange(NewMI, false)
2709 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
4759 MachineInstr *NewMI =
4762 MachineOperand &MO = NewMI->getOperand(X86::AddrIndexReg);
4774 MachineInstr *NewMI = addFrameReference(
4776 MachineOperand &MO = NewMI->getOperand(1 + X86::AddrIndexReg);
6295 MachineInstr *NewMI = BuildMI(MBB, MI, MIB->getDebugLoc(),
6303 assert(NewMI->getOperand(2).getReg() == X86::EFLAGS &&
6305 NewMI->getOperand(2).setIsUndef();
6306 assert(NewMI->getOperand(3).getReg() == X86::DF &&
6308 NewMI->getOperand(3).setIsUndef();
7186 MachineInstr &NewMI,
7191 for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
7192 MachineOperand &MO = NewMI.getOperand(Idx);
7201 Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
7206 NewMI.dump(); dbgs() << "\n");
7218 MachineInstr *NewMI =
7220 MachineInstrBuilder MIB(MF, NewMI);
7232 updateOperandRegConstraints(MF, *NewMI, TII);
7235 MBB->insert(InsertPt, NewMI);
7246 MachineInstr *NewMI =
7248 MachineInstrBuilder MIB(MF, NewMI);
7260 updateOperandRegConstraints(MF, *NewMI, TII);
7264 NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
7267 MBB->insert(InsertPt, NewMI);
7309 MachineInstr *NewMI =
7311 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
7312 return NewMI;
7331 MachineInstr *NewMI =
7333 return NewMI;
7346 MachineInstr *NewMI =
7348 return NewMI;
7353 if (auto *NewMI =
7356 return NewMI;
7468 MachineInstr *NewMI = nullptr;
7500 NewMI = IsTwoAddr ? fuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this)
7507 Register DstReg = NewMI->getOperand(0).getReg();
7509 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
7511 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
7513 return NewMI;
7525 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, Size,
7527 if (NewMI)
7528 return NewMI;
8323 MachineInstr *NewMI =
8326 if (NewMI)
8327 return NewMI;