Lines Matching full:tile
31 def TILELOADD#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
36 def TILELOADDT1#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
42 (ins sibmem:$dst, TILE:$src),
56 def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
65 def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
69 def PTILELOADDT1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
75 TILE:$src4), []>;
78 def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
79 [(set TILE:$dst, (int_x86_tilezero_internal
83 // Pseudo instructions, using immediates instead of tile registers.
101 def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
102 (ins TILE:$src1, TILE:$src2, TILE:$src3),
105 def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
106 (ins TILE:$src1, TILE:$src2, TILE:$src3),
109 def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
110 (ins TILE:$src1, TILE:$src2, TILE:$src3),
113 def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
114 (ins TILE:$src1, TILE:$src2, TILE:$src3),
121 def PTDPBSSDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
122 GR16:$src2, GR16:$src3, TILE:$src4,
123 TILE:$src5, TILE:$src6),
124 [(set TILE: $dst,
126 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
127 def PTDPBSUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
128 GR16:$src2, GR16:$src3, TILE:$src4,
129 TILE:$src5, TILE:$src6),
130 [(set TILE: $dst,
132 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
133 def PTDPBUSDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
134 GR16:$src2, GR16:$src3, TILE:$src4,
135 TILE:$src5, TILE:$src6),
136 [(set TILE: $dst,
138 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
139 def PTDPBUUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
140 GR16:$src2, GR16:$src3, TILE:$src4,
141 TILE:$src5, TILE:$src6),
142 [(set TILE: $dst,
144 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
148 // Pseudo instructions, using immediates instead of tile registers.
173 def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
174 (ins TILE:$src1, TILE:$src2, TILE:$src3),
180 def PTDPBF16PSV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
181 GR16:$src2, GR16:$src3, TILE:$src4,
182 TILE:$src5, TILE:$src6),
183 [(set TILE: $dst,
185 GR16:$src2, GR16:$src3, TILE:$src4,
186 TILE:$src5, TILE:$src6))]>;
189 // Pseudo instructions, using immediates instead of tile registers.
203 def TDPFP16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
204 (ins TILE:$src1, TILE:$src2, TILE:$src3),
211 def PTDPFP16PSV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
212 GR16:$src2, GR16:$src3, TILE:$src4,
213 TILE:$src5, TILE:$src6),
214 [(set TILE: $dst,
216 GR16:$src2, GR16:$src3, TILE:$src4,
217 TILE:$src5, TILE:$src6))]>;
232 def TCMMIMFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
233 (ins TILE:$src1, TILE:$src2, TILE:$src3),
236 def TCMMRLFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
237 (ins TILE:$src1, TILE:$src2, TILE:$src3),
244 def PTCMMIMFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
245 GR16:$src2, GR16:$src3, TILE:$src4,
246 TILE:$src5, TILE:$src6),
247 [(set TILE: $dst,
249 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
250 def PTCMMRLFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
251 GR16:$src2, GR16:$src3, TILE:$src4,
252 TILE:$src5, TILE:$src6),
253 [(set TILE: $dst,
255 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
276 I<Opcode, MRMSrcReg4VOp3, (outs TILE:$dst),
277 (ins TILE:$src1, TILE:$src2, TILE:$src3),
288 // Pseudo instructions, using immediates instead of tile registers.
309 def PTDPBF8PSV : PseudoI<(outs TILE:$dst),
311 TILE:$src4, TILE:$src5, TILE:$src6),
312 [(set TILE:$dst,
314 GR16:$src2, GR16:$src3, TILE:$src4,
315 TILE:$src5, TILE:$src6))]>;
316 def PTDPBHF8PSV : PseudoI<(outs TILE:$dst),
318 TILE:$src4, TILE:$src5, TILE:$src6),
319 [(set TILE:$dst,
321 GR16:$src2, GR16:$src3, TILE:$src4,
322 TILE:$src5, TILE:$src6))]>;
323 def PTDPHBF8PSV : PseudoI<(outs TILE:$dst),
325 TILE:$src4, TILE:$src5, TILE:$src6),
326 [(set TILE:$dst,
328 GR16:$src2, GR16:$src3, TILE:$src4,
329 TILE:$src5, TILE:$src6))]>;
330 def PTDPHF8PSV : PseudoI<(outs TILE:$dst),
332 TILE:$src4, TILE:$src5, TILE:$src6),
333 [(set TILE:$dst,
335 GR16:$src2, GR16:$src3, TILE:$src4,
336 TILE:$src5, TILE:$src6))]>;
373 def TTRANSPOSED : I<0x5f, MRMSrcReg, (outs TILE:$dst), (ins TILE:$src),
390 def PTTRANSPOSEDV : PseudoI<(outs TILE:$dst),
391 (ins GR16:$src1, GR16:$src2, TILE:$src),
392 [(set TILE: $dst,
394 TILE:$src))]>;
413 def TTDPBF16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
414 (ins TILE:$src1, TILE:$src2, TILE:$src3),
418 def PTTDPBF16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
419 GR16:$src2, GR16:$src3, TILE:$src4,
420 TILE:$src5, TILE:$src6),
421 [(set TILE: $dst,
423 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
431 def TTDPFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
432 (ins TILE:$src1, TILE:$src2, TILE:$src3),
436 def PTTDPFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
437 GR16:$src2, GR16:$src3, TILE:$src4,
438 TILE:$src5, TILE:$src6),
439 [(set TILE: $dst,
441 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
449 def TTCMMIMFP16PS : I<0x6b, MRMSrcReg4VOp3, (outs TILE:$dst),
450 (ins TILE:$src1, TILE:$src2, TILE:$src3),
453 def TTCMMRLFP16PS: I<0x6b, MRMSrcReg4VOp3, (outs TILE:$dst),
454 (ins TILE:$src1, TILE:$src2, TILE:$src3),
457 def TCONJTCMMIMFP16PS : I<0x6b, MRMSrcReg4VOp3, (outs TILE:$dst),
458 (ins TILE:$src1, TILE:$src2, TILE:$src3),
462 def TCONJTFP16 : I<0x6b, MRMSrcReg, (outs TILE:$dst), (ins TILE:$src),
466 def PTTCMMIMFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
467 GR16:$src2, GR16:$src3, TILE:$src4,
468 TILE:$src5, TILE:$src6),
469 [(set TILE: $dst,
471 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
472 def PTTCMMRLFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
473 GR16:$src2, GR16:$src3, TILE:$src4,
474 TILE:$src5, TILE:$src6),
475 [(set TILE: $dst,
477 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
478 def PTCONJTCMMIMFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
479 GR16:$src2, GR16:$src3, TILE:$src4,
480 TILE:$src5, TILE:$src6),
481 [(set TILE: $dst,
483 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
485 def PTCONJTFP16V : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2, TILE:$src3),
486 [(set TILE: $dst, (int_x86_tconjtfp16_internal GR16:$src1, GR16:$src2, TILE:$src3))]>;
524 def suffix : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src1),
526 def T1#suffix : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src1),
538 def PTILELOADDRSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
541 def PTILELOADDRST1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
556 (ins TILE:$src1, i32u8imm:$src2),
560 (ins TILE:$src1, GR32:$src2),
579 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
582 TILE:$src3, imm:$src4))]>;
584 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
587 TILE:$src3, GR32:$src4))]>;
589 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
592 TILE:$src3, imm:$src4))]>;
594 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
597 TILE:$src3, GR32:$src4))]>;
599 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
602 TILE:$src3, imm:$src4))]>;
604 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
607 TILE:$src3, GR32:$src4))]>;
609 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
612 TILE:$src3, imm:$src4))]>;
614 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
617 TILE:$src3, GR32:$src4))]>;
619 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
622 TILE:$src3, imm:$src4))]>;
624 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
627 TILE:$src3, GR32:$src4))]>;
636 (ins TILE:$src1, GR32:$src2),
641 (ins TILE:$src1, i32u8imm:$src2),
664 (ins TILE:$src1, u8imm:$src2),
668 (ins TILE:$src1, GR32:$src2),
687 (ins GR16:$src1, GR16:$src2, TILE:$src3, i32u8imm:$src4),
690 TILE:$src3, imm:$src4))]>;
692 (ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
695 TILE:$src3, GR32:$src4))]>;
702 def TMMULTF32PS: I<0x48, MRMSrcReg4VOp3, (outs TILE:$dst),
703 (ins TILE:$src1, TILE:$src2, TILE:$src3),
708 def PTMMULTF32PSV : PseudoI<(outs TILE:$dst),
710 TILE:$src4, TILE:$src5, TILE:$src6),
711 [(set TILE:$dst,
713 GR16:$src2, GR16:$src3, TILE:$src4,
714 TILE:$src5, TILE:$src6))]>;
728 def TTMMULTF32PS: I<0x48, MRMSrcReg4VOp3, (outs TILE:$dst),
729 (ins TILE:$src1, TILE:$src2, TILE:$src3),
734 def PTTMMULTF32PSV : PseudoI<(outs TILE:$dst),
736 TILE:$src4, TILE:$src5, TILE:$src6),
737 [(set TILE:$dst,
739 GR16:$src2, GR16:$src3, TILE:$src4,
740 TILE:$src5, TILE:$src6))]>;