Lines Matching defs:Arg1

436   Value *Arg1 = II.getArgOperand(1);
440   if (isa<UndefValue>(Arg0) && isa<UndefValue>(Arg1))
456   if (!isa<Constant>(Arg0) || !isa<Constant>(Arg1))
481   Arg1 = Builder.CreateSelect(Builder.CreateICmpSLT(Arg1, MinC), MinC, Arg1);
483   Arg1 = Builder.CreateSelect(Builder.CreateICmpSGT(Arg1, MaxC), MaxC, Arg1);
493   auto *Shuffle = Builder.CreateShuffleVector(Arg0, Arg1, PackMask);
503   Value *Arg1 = II.getArgOperand(1);
511   if (isa<UndefValue>(Arg0) || isa<UndefValue>(Arg1))
515   if (isa<ConstantAggregateZero>(Arg0) || isa<ConstantAggregateZero>(Arg1))
521       return IsSigned ? Builder.CreateAShr(Arg1, 15)
523     if (match(Arg1, m_One()))
529   if (!isa<Constant>(Arg0) || !isa<Constant>(Arg1))
537   Value *RHS = Builder.CreateCast(Cast, Arg1, ExtTy);
561   Value *Arg1 = II.getArgOperand(1);
571   if (isa<UndefValue>(Arg0) || isa<UndefValue>(Arg1))
575   if (isa<ConstantAggregateZero>(Arg0) || isa<ConstantAggregateZero>(Arg1))
579   if (!isa<Constant>(Arg0) || !isa<Constant>(Arg1))
595   auto *RHSLo = Builder.CreateShuffleVector(Arg1, LoMask);
596   auto *RHSHi = Builder.CreateShuffleVector(Arg1, HiMask);
2381     Value *Arg1 = II.getArgOperand(1);
2387     if (Value *V = SimplifyDemandedVectorEltsLow(Arg1, VWidth, 1)) {
2410         Value *Arg1 = II.getArgOperand(1);
2418           V = IC.Builder.CreateFAdd(Arg0, Arg1);
2422           V = IC.Builder.CreateFSub(Arg0, Arg1);
2426           V = IC.Builder.CreateFMul(Arg0, Arg1);
2430           V = IC.Builder.CreateFDiv(Arg0, Arg1);
2453         Value *Arg1 = II.getArgOperand(1);
2455         Value *RHS = IC.Builder.CreateExtractElement(Arg1, (uint64_t)0);
2572     Value *Arg1 = II.getArgOperand(1);
2573     assert(Arg1->getType()->getPrimitiveSizeInBits() == 128 &&
2575     unsigned VWidth = cast<FixedVectorType>(Arg1->getType())->getNumElements();
2577     if (Value *V = SimplifyDemandedVectorEltsLow(Arg1, VWidth, VWidth / 2)) {
2685       Value *Arg1 = II.getArgOperand(1);
2702               IC.SimplifyDemandedVectorElts(Arg1, DemandedElts2, UndefElts2)) {
3278       Value *Arg0 = II.getArgOperand(0), *Arg1 = II.getArgOperand(1);
3280           IsSubOnly ? Instruction::FSub : Instruction::FAdd, Arg0, Arg1);