Lines Matching defs:Ins

1103     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1112   CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1302                                     const SmallVectorImpl<ISD::InputArg> &Ins,
1307   ISD::ArgFlagsTy Flags = Ins[i].Flags;
1341   EVT ArgVT = Ins[i].ArgVT;
1356     if (Ins[i].PartOffset == 0) {
1385                       DAG.getIntPtrConstant(Ins[i].PartOffset, dl));
1388                              DAG.getMachineFunction(), FI, Ins[i].PartOffset));
1680     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1706   CCInfo.AnalyzeArguments(Ins, CC_X86);
1711     CCInfo.AnalyzeArgumentsSecondPass(Ins, CC_X86);
1722     assert(InsIndex < Ins.size() && "Invalid Ins index");
1809           LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, InsIndex);
1814         !(Ins[I].Flags.isByVal() && VA.isRegLoc())) {
1822   for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
1823     if (Ins[I].Flags.isSwiftAsync()) {
1849     if (Ins[I].Flags.isSRet()) {
1876   } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
1883     if (!canGuaranteeTCO(CallConv) && hasCalleePopSRet(Ins, Subtarget))
1919     for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
1920       if (Ins[I].Flags.isSwiftSelf() || Ins[I].Flags.isSwiftAsync() ||
1921           Ins[I].Flags.isSwiftError()) {
2006   SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
2601   return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl, DAG,
2755   const SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2832   for (const auto &In : Ins) {
2841     RVCCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2849   if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,