Lines Matching defs:XOR
2693 ISD::XOR,
2741 // Currently only MSVC CRTs XOR the frame pointer into the stack guard value.
5294 if (V.getOpcode() == ISD::XOR &&
8606 case ISD::XOR:
13969 // the inputs, place the other input in it. We use (Index XOR 1) to
17885 case ISD::XOR:
20436 // to XOR'ing the high 32 bits with Adjust.
20524 // If we need an unsigned fixup, XOR the result with adjust.
20526 Res = DAG.getNode(ISD::XOR, DL, MVT::i64, Res, Adjust);
22418 return X.getOpcode() == ISD::XOR;
22437 if (X.getOpcode() == ISD::XOR) {
22443 return DAG.getNode(ISD::XOR, DL, VecVT, A, B);
22483 // Use XOR (plus OR) and PTEST after SSE4.1 for 128/256-bit operands.
22564 Cmp = DAG.getNode(ISD::XOR, DL, VecVT, VecX, VecY);
22714 DAG.getNode(ISD::XOR, DL, MVT::i32, SplitLHS.first, SplitRHS.first);
22716 DAG.getNode(ISD::XOR, DL, MVT::i32, SplitLHS.second, SplitRHS.second);
22777 // Convert to a ICMP_EQ(XOR(LHS,RHS),0) pattern.
22778 SDValue V = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
22802 SDValue V = DAG.getNode(ISD::XOR, DL, TestVT, LHS, RHS);
23038 case ISD::XOR:
23048 case ISD::XOR: Opcode = X86ISD::XOR; break;
23059 case X86ISD::XOR:
23603 // probably cheaper than XOR+PCMPGT using 2 different vector constants:
24030 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v2i64, Op0, SB);
24031 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v2i64, Op1, SB);
24087 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SM);
24088 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SM);
24438 Opc == X86ISD::OR || Opc == X86ISD::XOR || Opc == X86ISD::AND))
24484 // SELECT (AND(X,1) == 0), C1, C2 -> XOR(C1,AND(NEG(AND(X,1)),XOR(C1,C2))
24488 SDValue Diff = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
24490 return DAG.getNode(ISD::XOR, DL, VT, LHS, Flip);
24499 case ISD::XOR:
24538 // SELECT (AND(X,1) == 0), Y, (XOR Y, Z) -> (XOR Y, (AND NEG(AND(X,1)), Z))
28721 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
28808 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, X, SignMask);
29974 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
30036 Res = DAG.getNode(ISD::XOR, dl, VT, Res, SignMask);
30138 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
30370 DAG.getNode(ISD::XOR, dl, VT, Masked, SignBitMask);
31489 // If atomic XOR/OR need to be setting and testing the same bit.
32444 X = DAG.getNode(ISD::XOR, DL, MVT::i32, Lo, Hi);
32451 X = DAG.getNode(ISD::XOR, DL, MVT::i32, X, Hi16);
32464 SDValue Flags = DAG.getNode(X86ISD::XOR, DL, VTs, Lo, Hi).getValue(1);
34703 NODE_NAME_CASE(XOR)
38037 (Opcode == ISD::OR || Opcode == ISD::XOR || Opcode == X86ISD::ANDNP) &&
44561 case ISD::XOR:
44577 // Helper to flip between AND/OR/XOR opcodes and their X86ISD FP equivalents.
44583 case ISD::XOR: return X86ISD::FXOR;
44611 case ISD::XOR:
44634 case ISD::XOR:
44844 Op.getOpcode() != ISD::XOR)
45012 case ISD::XOR: {
45298 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
45513 MinPos = DAG.getNode(ISD::XOR, DL, SrcVT, Mask, MinPos);
45532 MinPos = DAG.getNode(ISD::XOR, DL, SrcVT, Mask, MinPos);
45551 // Check for OR(any_of)/AND(all_of)/XOR(parity) horizontal reduction patterns.
45555 Match = DAG.matchBinOpReduction(Extract, BinOp, {ISD::XOR});
45651 if (BinOp == ISD::XOR) {
46990 SDValue SubOp1 = DAG.getNode(ISD::XOR, DL, MaskVT, V, Mask);
47645 // - XOR/OR/AND (if they were made to survive AtomicExpand)
47764 // TODO: XOR(X,Y) -> see if only one operand contributes to the signbit.
48300 // MOVMSK(PCMPEQ(X,Y)) == -1 -> PTESTZ(XOR(X,Y),XOR(X,Y)).
48301 // MOVMSK(PCMPEQ(X,Y)) != -1 -> !PTESTZ(XOR(X,Y),XOR(X,Y)).
48308 SDValue V = DAG.getNode(ISD::XOR, SDLoc(BC), BC.getValueType(),
48319 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), LHS.getValueType(),
48321 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), RHS.getValueType(),
48363 SDValue V = DAG.getNode(ISD::XOR, DL, Result.getValueType(),
50309 // Try to widen AND, OR and XOR nodes to VT in order to remove casts around
50407 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
50421 assert((Opc == ISD::OR || Opc == ISD::AND || Opc == ISD::XOR) &&
50482 assert((Opc == ISD::OR || Opc == ISD::AND || Opc == ISD::XOR) &&
50514 assert((Opc == ISD::OR || Opc == ISD::AND || Opc == ISD::XOR) &&
50551 assert((Opc == ISD::OR || Opc == ISD::AND || Opc == ISD::XOR) &&
50889 // Opc must be ISD::AND or ISD::XOR
50896 // Opc must be ISD::AND or ISD::XOR
50913 assert(N->getOpcode() == ISD::AND || N->getOpcode() == ISD::XOR);
51426 // TODO: Attempt to match against AND(XOR(-1,M),Y) as well, waiting for
51604 SDValue Xor0 = DAG.getNode(ISD::XOR, DL, VT, And1_R, Freeze_And0_R);
51606 SDValue Xor1 = DAG.getNode(ISD::XOR, DL, VT, And, Freeze_And0_R);
51616 // Note that masked-merge variants using XOR or ADD expressions are
51853 assert((Opc == ISD::XOR || Opc == ISD::OR) && "Unexpected opcode");
51859 // where imm is odd if and only if we have xor, in which case the XOR/OR are
51864 bool IsSub = Opc == ISD::XOR;
51873 if (Opc == ISD::XOR && N0.getOpcode() == X86ISD::PCMPEQ &&
52047 /// XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
52885 unsigned SignOp = ISD::XOR;
53431 SDValue XOR = LHS.getOperand(0);
53432 if (XOR->getOpcode() == ISD::XOR && XOR.hasOneUse()) {
53433 KnownBits XORRHS = DAG.computeKnownBits(XOR.getOperand(1));
53628 case ISD::XOR:
53982 case ISD::XOR:
53987 // For XOR and FXOR, we want to check if constant
54208 case X86ISD::FXOR: IntOpcode = ISD::XOR; break;
54220 if (N->getOpcode() != ISD::XOR)
54235 assert((N->getOpcode() == ISD::XOR || N->getOpcode() == ISD::SUB) &&
54369 return DAG.getNode(ISD::XOR, DL, VT, LHS,
54370 DAG.getNode(ISD::XOR, DL, VT, RHS, N1));
54423 N0 = DAG.getNode(ISD::XOR, DL, VT, N0, SignMask);
54424 N1 = DAG.getNode(ISD::XOR, DL, VT, N1, SignMask);
54425 return DAG.getNode(ISD::XOR, DL, VT,
54735 // ANDNP(x, -1) -> NOT(x) -> XOR(x, -1)
55812 return DAG.getNode(ISD::XOR, DL, VT,
55823 return DAG.getNode(ISD::XOR, DL, VT,
55856 SDValue Res = DAG.getNode(ISD::XOR, DL, SrcVT, ShiftLHS, ShiftRHS);
56572 case ISD::XOR: NewOpc = X86ISD::XOR; break;
57272 // negation into a preceding instruction. If the RHS of the sub is a XOR with
57276 if (Op1.getOpcode() == ISD::XOR && IsNonOpaqueConstant(Op0) &&
57279 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT, Op1.getOperand(0),
57834 case ISD::XOR:
59373 case ISD::XOR: return combineXor(N, DAG, DCI, Subtarget);
59584 case ISD::XOR:
59712 case ISD::XOR: